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National Instruments PCIe-7846R Manual

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USER MANUAL

NI PCIe-7846

R Series Digital I/O Module for PCI Express, 8 AI, 8 AO, 48 DIO,

500 kS/s AI, Kintex-7 160T FPGA

This document provides compliance, pinout, connectivity, mounting, and power information

for the PCIe-7846.

Hardware Overview

The following high-level block diagram represents the PCIe-7846.

Figure 1. PCIe-7846 Block Diagram

NI ASIC

FPGA

NI PCIe-7846

DIO

Data/

Address/

Control

AO (x8)

ADC AI

AI (x8)

INA

DIO (x16)

DIO (x32)

DDR3 RAM

Kintex-7

DAC

+5 V

Reference

CONNECTOR 1

(DIO)

CONNECTOR 0

(MIO)

Device

Temperature

Flash

Memory

100 MHz

OSC

PCIe Connector

Overvoltage

Protection

Overvoltage

Protection

Overvoltage

Protection

Overvoltage

Protection

Pinout

DIO30

GND

DIO28

GND

DIO26

GND

DIO24

GND

DIO22

GND

DIO20

GND

DIO18

GND

DIO16

GND

DIO14

GND

DIO12

GND

DIO10

GND

DIO8

GND

DIO6

GND

DIO4

GND

DIO2

GND

DIO0

GND

EXTCLKIN

GND

DIO31

DIO29

GND

DIO25

GND

DIO23

GND

DIO27

GND

DIO21

GND

DIO19

GND

DIO17

GND

DIO15

GND

DIO13

GND

DIO11

GND

DIO9

GND

DIO7

GND

DIO5

GND

DIO3

GND

DIO1

GND

68 34

67 33

66 32

65 31

64 30

63 29

62 28

61 27

60 26

59 25

58 24

57 23

56 22

55 21

54 20

53 19

52 18

51 17

50 16

49 15

48 14

47 13

46 12

45 11

44 10

43 9

42 8

41 7

40 6

39 5

38 4

37 3

36 2

35 1

+5V

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

DIO6

DIO7

DIO9

DIO11

DIO13

DIO15

AO7

AO6

AO5

AO4

AO3

AO2

AO1

AO0

AISENSE

AI7+

AIGND6

AI6+

AI5+

AIGND4

AI4+

AI3+

AIGND2

AI2+

AI1+

AIGND0

AI0+

+5V

DGND

DIO8

DIO10

DIO12

DIO14

AOGND7

AOGND6

AOGND5

AOGND4

AOGND3

AOGND2

AOGND1

AOGND0

AI7–

AIGND7

AI6–

AI5–

AIGND5

AI4–

AI3–

AIGND3

AI2–

AI1–

AIGND1

AI0–

68 34

67 33

66 32

65 31

64 30

63 29

62 28

61 27

60 26

59 25

58 24

57 23

56 22

55 21

54 20

53 19

52 18

51 17

50 16

49 15

48 14

47 13

46 12

45 11

44 10

43 9

42 8

41 7

40 6

39 5

38 4

37 3

36 2

35 1

CONNECTOR 1

(DIO)

CONNECTOR 0

(MIO)

TERMINAL 34

TERMINAL 68

TERMINAL 1

TERMINAL 35

TERMINAL 34

TERMINAL 68

TERMINAL 1

TERMINAL 35

Table 1. PCIe-7846 Signal Descriptions

Signal Description

AI+ Positive analog input signal connection

AI- Negative analog input signal connection

AISENSE Reference connection for NRSE measurements

AIGND Ground reference for the analog input signal

AO Analog output signal connection

AOGND Ground reference for the analog output signal

2| ni.com | NI PCIe-7846 User Manual

Table 1. PCIe-7846 Signal Descriptions (Continued)

Signal Description

DIO Digital input/output signal connection

DGND Ground reference for the digital signal

EXTCLKIN External clock input source that can be used for source synchronous

acquisitions. The provided clock source must be stable and glitch-free.

GND Ground connection

Supply (+5 Vout) 5 V power output connection for external devices

NC No connection

The PCIe-7846 is protected from overvoltage and overcurrent conditions.

Note Refer to the device specifications, available at ni.com/manuals for more

information.

Analog Input

The PCIe-7846 provides connections for eight AI channels. Each channel has an AI+ pin, AI-

pin, and AIGND pin to which you can connect both single-ended or differential voltage

signals. Use the AISENSE pin to connect non-referenced single-ended signals.

Connecting Single-Ended Voltage Signals

To connect referenced single-ended voltage signals to the PCIe-7846, you must connect the

voltage ground signal to AI GND in order to keep the common-mode voltage in the specified

range.

Figure 2. Connecting Referenced Single-Ended Signals to the PCIe-7846

PGIA ADC

AI+

NI PCIe-7846

Connection

Accessory

AISENSE

AIGND

–

Overvoltage

Protection

AI– Overvoltage

Protection

Overvoltage

Protection

NI PCIe-7846 User Manual | © National Instruments | 3

To connect non-referenced single-ended voltage signals to the PCIe-7846, you must connect

the voltage ground signal to AI SENSE in order to keep the common-mode voltage in the

specified range.

Figure 3. Connecting Non-Referenced Single-Ended Signals to the PCIe-7846

PGIA ADC

AI+

NI PCIe-7846

Connection

Accessory

AISENSE

AIGND

Vcm

–

Overvoltage

Protection

AI– Overvoltage

Protection

Overvoltage

Protection

Connecting Differential Voltage Signals

You can connect grounded or floating differential signal sources to the PCIe-7846. Connect the

positive voltage signal to the AI+ and the negative voltage signal to AI-. To connect grounded

differential signals to the PCIe-7846, you must also connect the signal reference to AI GND.

Figure 4. Connecting Grounded Differential Signals to the PCIe-7846

PGIA ADC

AI+

NI PCIe-7846

Connection

Accessory

AISENSE

AIGND

Vcm

–

Overvoltage

Protection

AI– Overvoltage

Protection

Overvoltage

Protection

To connect floating differential signals to the PCIe-7846, you must connect the negative and

positive signals to AI GND through 1 MΩ resistors to keep the voltage within the common-

mode voltage range. If the voltage source is outside the common-mode voltage range, the

PCIe-7846 does not read data accurately.

4| ni.com | NI PCIe-7846 User Manual

Figure 5. Connecting Floating Differential Signals to the PCIe-7846

1 MΩ

Resistor

1 MΩ

Resistor

1 MΩ

Resistor

1 MΩ

Resistor

–

PGIA ADC

AI+

NI PCIe-7846

Connection

Accessory

AISENSE

AIGND

Overvoltage

Protection

AI– Overvoltage

Protection

Overvoltage

Protection

Analog Output

The PCIe-7846 provides connections for eight analog output channels. Each channel has an

AO pin and AOGND pin to which you can connect a load.

Figure 6. Connecting a Load

NI PCIe-7846

Connection

Accessory

AOGND

LOAD

DAC

Digital I/O

The NI PCIe-7846 provides connections for 48 digital input/output (DIO) channels. Connector

0 contains 16 low-speed channels that can run up to 10 MHz signal frequencies. Connector 1

contains 32 high-speed DIO channels that can run up to 80 MHz signal frequencies and

support external clock source. Each connector has selectable logic levels that you can

configure as 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V. You can configure each channel as input or

output.

NI PCIe-7846 User Manual | © National Instruments | 5

Figure 7. Connecting to the DIO Channels

NI PCIe-7846

Power

FPGA

Connection

Accessory

DIO0

DIO1

DIO14

DIO15

Connecter 0 (MIO)

Connection

Accessory

DIO0

DIO1

DIO30

DIO31

Connecter 1 (DIO)

1. Low-speed signal frequencies up to 10 MHz with logic levels configured as 1.2 V, 1.5 V, 1.8 V, 2.5 V, or

3.3 V.

2. High-speed signal frequencies up to 80 MHz with logic levels configured as 1.2 V, 1.5 V, 1.8 V, 2.5 V, or

3.3 V.

3. LED

The DIO channels have overvoltage and undervoltage protection as well as over current

protection. Refer to the device specifications on ni.com/manuals for more information about

the maximum voltage and current.

When the system powers on, the DIO channels are set as input low with pull-down resistors.

To set another power-on state, you can configure the NI PCIe-7846 to load a VI when the

system powers on. The VI can then set the DIO lines to any power-on state.

All the high-speed DIO channels on Connector 1 are routed with a 50 Ω characteristic trace

impedance. Route all external circuitry with a similar impedance to ensure best signal quality.

NI recommends performing signal integrity measurements to test the affect of signal routing

with the cable and connection accessory for your application.

Field Wiring Considerations

Environmental noise can seriously affect the measurement accuracy of the device if you do not

take proper care when running signal wire between signal sources and the device. The

following recommendations mainly apply to AI signal routing to the device, as well as signal

routing in general.

6| ni.com | NI PCIe-7846 User Manual

Take the following precautions to minimize noise pickup and maximize measurement

accuracy:

• Use differential AI connections to reject common-mode noise.

• Use individually shielded, twisted-pair wires to connect AI signals to the device. With

this type of wire, the signal attached to the positive and negative inputs are twisted

together and then covered with a shield. You then connect this shield only at one point to

the signal source ground. This kind of connection is required for signals traveling through

areas with large magnetic fields or high electromagnetic interference.

• Route signals to the device carefully. Keep cabling away from noise sources, such as

video monitors and analog signals.

Use the following recommendations for all signal connections to the NI PCIe-7846:

• Separate NI PCIe-7846 signal lines from high-current or high-voltage lines. These lines

can induce currents in or voltages on the NI PCIe-7846 signal lines if they run in parallel

paths at a close distance. To reduce the magnetic coupling between lines, separate them

by a reasonable distance if they run in parallel or run the lines at right angles to each

other.

• Do not run signal lines through conduits that also contain power lines.

• Protect signal lines from magnetic fields caused by electric motors, welding equipment,

breakers, or transformers by running them through special metal conduits.

• To minimize signal-to-signal skew within each digital channel, maintain signal lines'

length within 1 inch of difference.

+5 V Power Source

Use the +5 V terminals on the I/O connector supply +5 V referenced to DGND to power

external circuitry.

Caution Never connect the +5 V power terminals to analog or digital ground or

any other voltage source on the NI PCIe-7846 or any other device. Doing so can

damage the device and the computer. National Instruments is not liable for damage

resulting from such a connection.

The power rating is 4.75 to 5.1 V DC at 0.5 A.

On-board Flash Memory

The PCIe-7846 includes a flash memory on-board, allowing users to store their FPGA bitfile

in the flash memory with NI MAX. The user FPGA bitfile will be loaded from the flash

memory after a system power cycle. For more information on downloading a bitfile to NI

FPGA target, visit ni.com/info and enter the Info Code dwnbitfile.

Monitoring the Device Temperature

You can monitor the device temperature through the onboard temperature sensor of the

PCIe-7846 using an FPGA I/O Node. After adding an FPGA I/O Node to the block diagram,

click the element section of the node, and select Device Temperature. The return value is in

increments of 0.25 °C. For more details, refer to the NI PCIe-7846 Reference topic in

LabVIEW Help.

Worldwide Support and Services

The NI website is your complete resource for technical support. At ni.com/support, you have

access to everything from troubleshooting and application development self-help resources to

email and phone assistance from NI Application Engineers.

Visit ni.com/services for information about the services NI offers.

Visit ni.com/register to register your NI product. Product registration facilitates technical

support and ensures that you receive important information updates from NI.

NI corporate headquarters is located at 11500 North Mopac Expressway, Austin, Texas,

78759-3504. NI also has offices located around the world. For support in the United States,

create your service request at ni.com/support or dial 1 866 ASK MYNI (275 6964). For

support outside the United States, visit the Worldwide Offices section of ni.com/niglobal to

access the branch office websites, which provide up-to-date contact information.

Information is subject to change without notice. Refer to the NI Trademarks and Logo Guidelines at ni.com/trademarks for

information on NI trademarks. Other product and company names mentioned herein are trademarks or trade names of their

respective companies. For patents covering NI products/technology, refer to the appropriate location: Help»Patents in your

software, the patents.txt file on your media, or the National Instruments Patent Notice at ni.com/patents. You can find

information about end-user license agreements (EULAs) and third-party legal notices in the readme file for your NI product. Refer

to the Export Compliance Information at ni.com/legal/export-compliance for the NI global trade compliance policy and how

to obtain relevant HTS codes, ECCNs, and other import/export data. NI MAKES NO EXPRESS OR IMPLIED WARRANTIES AS

TO THE ACCURACY OF THE INFORMATION CONTAINED HEREIN AND SHALL NOT BE LIABLE FOR ANY ERRORS. U.S.

Government Customers: The data contained in this manual was developed at private expense and is subject to the applicable

limited rights and restricted data rights as set forth in FAR 52.227-14, DFAR 252.227-7014, and DFAR 252.227-7015.

378050A-03 November 5, 2018

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