ON Semiconductor KAI-2093 Manuale utente

©Semiconductor Components Industries, LLC, 2014

October, 2014 − Rev. 2 1Publication Order Number:

EVBUM2277/D

KAI-2093 Image Sensor

Evaluation Timing

Specification

12-bit 20 MHz AFE

Altera Code Version Description

The Altera code described in this document is intended for

use in the KSC−1000 Timing Boar. The code is developed

specifically for use with the following system configuration:

Table 1. SYSTEM CONFIGURATION

Evaluation Board Kit PN 4H0706

Timing Generator Board PN 3F5051 (AD9845A 20 MHz)

KAI−2001/KAI−2020/KAI−2093 CCD Imager Board PN 3F5121

Framegrabber Board National Instruments Model PCI−1424

The 3F5051 Timing Generator Board features the

KSC−1000 Timing Generator chip. The KSC−1000

provides all of the signals necessary for an imaging system

using Full Frame (KAF) or Interline (KAI) family of image

sensors. It also provides the signals necessary for operation

of two analog front-end (AFE) chips, enabling independent

optimization of the AFE chips for dual channel readout

devices.

ALTERA CODE FEATURES/FUNCTIONS

The Altera Programmable Logic Device (PLD) serves as

a state machine, which performs a variety of functions.

Three basic functions are required, common to all CCD

image sensor configurations: serial input steering, AFE

default programming, and KSC−1000 default

programming. In addition, certain other functions specific to

the KAI−2093 Image Sensor are implemented.

Serial Input Steering

The 3-wire serial interface enters the Timing Board

through the DIO Interface connector, and is routed to the

PLD. The Altera PLD decodes the addressing of the serial

input, and steers the datastream to the correct device.

The serial input must be formatted so that the Altera PLD

can correctly decode and steer the data to the correct device.

The serial interface can be used to dynamically change the

operating conditions of the AFE or KSC−1000 chips by

reprogramming the appropriate registers. Reprogramming

these registers through the serial interface will have no effect

on the default settings that are automatically programmed

into these devices on power-up or board reset.

Table 2. SERIAL INPUT DEVICE SELECT

Device Select DS[2..0] Serial Device

000 PLD

001 AFE1

010 AFE2

011 KSC−1000

100 (Not Used)

101 (Not Used)

110 (Not Used)

111 (Not Used)

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Figure 1. Serial Input Timing

SLOAD_INPUT

SDATA_INPUT

SCLK_INPUT

DS2

DS1

DS0

R/W

A3 (or Test)

…

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

(decoded PLD output)

SLOAD_xxx

The first 3 bits in the datastream are the Device Select bits

DS[2..0], sent MSB first, as shown in Figure 1. The Device

Select bits are decoded as shown in Table 2.

The next bit in the datastream is the Read/Write bit (R/W).

Only writing is supported; therefore this bit is always LOW.

The definition of next four bits in the datastream depends

on the device being addressed with the Device Select bits.

For the KSC−1000 device, they are Register address bits

A[0..3], LSB first. For the AD9845A AFE, they are Register

Address bits A[0..2], LSB first, followed by a Test bit which

is always set LOW.

The remaining bits in the bitstream are Data bits, LSB

first, with as many bits as are required to fill the appropriate

AFE Default Initialization

Upon power up, or when the BOARD_RESET button is

pressed, the PLD programs the registers of the two AFE

chips on the Timing Generator Board to their default settings

via the 3-wire serial interface. See Table 9 for details.

The AD9845A AFE must be reprogrammed on power-up,

as it does not retain register settings when power is removed.

Figure 2. AFE Initialization Timing

R/W

Test

ÏÏÏÏÏÏÏ

SLOAD_AFE_x

SDATA

SCLK

D10

The data for each AFE register is formatted into two bytes

of data, as shown in Figure . The Read/Write bit is always

low, and the Address bits specify the register being

programmed, as shown in Table 9. Each byte is read into an

8-bit shift register, and is shifted out as a serial stream of

eight bits. Each register in the AFE is programmed in this

fashion until the entire AFE is programmed.

KSC−1000 Default Initialization

Upon power-up, or when the BOARD_RESET button is

pressed, the Altera PLD programs the registers of the

KSC−1000 chip on the AFE Timing Generator Board to

their default settings via the 3-wire serial interface.

The default settings are selected by the user through the PLD

inputs SW[7..0] and DIO[15..0] (See Table 10 through

Table 24 for details). The KSC−1000 must be

reprogrammed on power-up, as it does not retain register

settings when power is removed.

The KSC−1000 default settings automatically

programmed by the PLD allow the Evaluation Board Kit

user to operate the CCD image sensor with minimal

intervention and no programming. The default settings are

chosen to comply with the CCD device specification (See

References). The registers, line tables and frame tables

described in this document also serve as examples for those

who wish to create their own KSC−1000 timing.

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Figure 3. KSC−1000 Initialization Timing

R/W

SLOAD_TG

SDATA

SCLK

ÏÏ

ÏÏÏÏÏÏÏ

…

[Dummy Bits]

The data for each KSC−1000 register is formatted into

bytes of data, as shown in Figure 3. The Read/Write bit is

always low, and the Address bits specify the register being

programmed, as shown in Table 3. Each byte is read into an

8-bit shift register, and is shifted out of the PLD as a serial

stream of eight bits. The last byte of data sent to a particular

the SLOAD_TG signal is brought HIGH at the appropriate

time so that the correct number of bits are streamed into each

KSC−1000 is programmed in this fashion until the entire

device is programmed.

Table 3. KSC−1000 REGISTERS

0Frame Table Pointer 3

1General Setup 202

2General Control 2

3INTG_STRT Setup 30

4INTG_STRT Line 13

5Signal Polarity 25

6 Offset 78

7 Width 65

8Frame Table Access (Variable)

9Line Table Access (Variable)

PLD State Machine

The Altera PLD contains a State Machine that parallels

the operation of the KSC−1000. The PLD controls the

KSC−1000 through the VD_TG output, and monitors

several of the KSC−1000 outputs, enabling it to track and

control the operation of the Timing Generator.

Remote Board Reset

The DIO14 input is used as a remote Board Reset control

line. The Altera PLD monitors this input, and when DIO14

goes HIGH, the ARSTZ (active low) output to the

KSC−1000 is asserted, disabling and clearing the timing

generator. When DIO14 goes LOW, the ARSTZ output is

de-asserted, and the Power-up/Board Reset initialization

sequence is executed. This allows programmable control of

the timing sequences to change the Electronic Shutter

position, for example.

Integration Clock

The Altera PLD uses the System Clock and an internal

counter to generate a1.0 ms-period clock. This clock is used

to generate an internal delay after power-up or Board Reset.

It may also be used to control precise integration times for

the image sensor.

Output Channel Control

PLD input SW0 is used to select one of the supported

operation modes: Full Field Single Output, and Full Field

Dual Output. When making a change to the switch settings,

the user must initiate a Board Reset for the change to take

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effect, either by pressing the BOARD_RESET button (S1)

on the Timing Board, or by setting and resetting the Remote

Reset (DIO14) input.

Integration & Electronic Shutter Control

In the Full Field Timing Modes, PLD inputs DIO[11..7]

may be used to select the integration time. See Table 25 for

timing details. In general, when making a change to the

DIO[11..7] settings, the user must initiate a Board Reset for

the change to take effect, either by pressing the

BOARD_RESET button (S1) on the Timing Board, or by

setting and resetting the Remote Reset (DIO14) input.

Binning Control

PLD input SW2 is used to select between 2×2 Binning

Single Output, and normal operation (no binning). When

making a change to the switch settings, the user must initiate

a Board Reset for the change to take effect, either by pressing

the BOARD_RESET button (S1) on the Timing Board, or

by setting and resetting the Remote Reset (DIO14) input.

Video Mux Switch

The PLD input SW6 controls the Video Mux Switch,

which steers either CCD output VoutL or VoutR to the

auxiliary video output connector J1.

ALTERA CODE I/O

Inputs

The Altera PLD has multiple inputs that may be used to

control certain functions. The inputs include: user selectable

switches SW[7..0] on the Timing Board; remote digital

inputs DIO[15..0] and a 3-wire serial interface through

Timing Board connector J7; Timing Board signals;

and various outputs from the KSC−1000 Timing Generator.

The KSC−1000 outputs are monitored by the PLD to control

auxiliary timing functions, and keep the KSC−1000 and

Altera PLD synchronized. The remote digital inputs

DIO[15..0] are optional, and are not required for KAI−2093

operation, but may be used to control integration time and

remote triggering.

Table 4. ALTERA INPUTS

Symbol Description

POWER_ON_DELAY The Rising Edge of this Signal Clears and Re-initializes the PLD

SYSTEM_CLK 40 MHz Clock, 2X the Desired Pixel Clock Rate

PIXCLK NI1424 20 MHz Pixel Rate Clock from the KSC1000TG (Not Used)

SW0 HIGH = Dual Output, Full Image, LOW = Single Output, Full Image

SW1 (Not Used, Must be LOW)

SW2 Binning Mode: HIGH = 2 x 2 Binning, Single Output, LOW = No Binning

SW3 (Not Used)

SW4 (Not Used)

SW5 (Not Used)

SW6 Video Mux Switch Control: HIGH = VoutR, LOW = VoutL

SW7 (Not Used)

DIO[6..0] (Not Used)

DIO[11..7] Integration Control (See Table 24)

DIO12 (Not Used)

DIO13 (Not Used)

DIO14 Remote Board Reset (HIGH Activates ARSTZ, Falling Edge Activates BOARD_RESET)

SLOAD_INPUT 3-wire Serial Interface LOAD Signal Input

SDATA_INPUT 3-wire Serial Interface DATA Signal Input

SCLOCK_INPUT 3-wire Serial Interface CLOCK Signal Input

LINE_VALID Used to Monitor KSC−1000

FRAME_VALID Used to Monitor KSC−1000

AUX_SHUT (Not Used for KAI−2093 Operation)

INTG_START Used to Monitor KSC−1000

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Outputs

The Altera PLD outputs include: the 3-wire serial

interface; control signals to the KSC−1000;

the INTEGRATE signal used for external monitoring and

synchronization; the PLD[2..0] signals which are auxiliary

Imager Board control bits; and the GIO[2..0] bits which are

used for PLD monitoring and testing.

Table 5. ALTERA OUTPUTS

Symbol Description

PLD_OUT0 KAI−2093 Video MUX Control

PLD_OUT1 (Not Used for KAI−2093 Operation)

PLD_OUT2 (Not Used for KAI−2093 Operation)

GIO[2..0] (Not Used for KAI−2093 Operation)

SLOAD_AFE_1 Serial Load Enable, Ch1 AD9845A AFE

SLOAD_AFE_2 Serial Load Enable, Ch2 AD9845A AFE

SLOAD_TG Serial Load Enable, KSC−1000

SDATA 3-wire Serial Interface DATA Signal Output

SCLOCK 3-wire Serial Interface CLOCK Signal Output

INTEGRATE High During CCD Integration Time

HD_TG (Not Used for KAI−2093 Operation)

VD_TG Control Signal to KSC−1000

ARSTZ Asynchronous Reset to KSC−1000 (from DIO14)

KAI−2093 TIMING CONDITIONS

System Timing Conditions

Table 6. SYSTEM TIMING

Description Symbol Time Notes

System Clock Period Tsys 25.0 ns 40 MHz System Clock

Unit Integration Time Uint 1.0 ms Generated by PLD

Power Stable Delay Tpwr 100 ms Typical

Default Serial Load Time Tsload 2.06 ms Typical

Integration Time Tint Operating Mode Dependent

CCD Timing Conditions

Table 7. CCD TIMING

Description Symbol Time Pixel

Counts Notes

H1, H2, RESET Period Tpix 50.0 ns 1 20 MHz Clocking of H1, H2, RESET

VCCD Delay TVD 50.0 ns 1 Delay after Hclks Stop

VCCD Transfer Time TVCCD 1.75 ms35 V2 Rising Edge to V2 Falling Edge

HCCD Delay THD 1.55 ms31 Delay before Hclks Resume

Vertical Transfer Period Vperiod 3.35 ms67 Vperiod = TVD + TVCCD +THD

Horizontal Pixels HPIX 100.80 ms2016 1992 CCD Pixels + 24 Overclock Pixels

Vertical Pixels VPIX 1220 1214 CCD Lines + 6 Overclock Lines

Line Transfer Time TL104.15 ms2083 TL = Vperiod + HPIX

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Table 7. CCD TIMING (continued)

Description Notes

Pixel

Counts

TimeSymbol

VCCS Pedestal Time T3P 25.05 ms501

Photodiode Transfer Time TV3rd 12.30 ms246 V2 3rd Level

Photodiode Delay T3D 20.00 ms400

Photodiode Frame Delay T3FD 85.50 ms1710 Delay before 1st Line Transfer

Photodiode Transfer Period T3PT142.85 ms2857 T3PT = T3P + TV3rd + T3D + T3FD

Shutter Pulse Setup TEL 1.50 ms30

Shutter Pulse Time TS10.0 ms200

Shutter Pulse Delay TSD 1.50 ms30

PCI−1424 Timing Conditions

Table 8. PCI−1424 TIMING

Description Symbol Time Pixel

Counts Notes

PIX Period TPIX 50.0 ns 1 20 MHz Clocking of DATACLK Sync Signal

FRAME Time TFRAME 127.2 ms 2,544,117 TFRAME = TPIX * ((Vperiod + HPIX) * VPIX + T3PT)

MODES OF OPERATION

The following modes of operation are available to the

user:

Electronic Shutter Modes

The Evaluation Board electronic shutter circuitry

provides a method of precisely controlling the image

exposure time without any mechanical components. Charge

may be cleared from the CCD photodiodes at some time

during the readout of the previous frame. This allows

integration times of less than one frame time, to compensate

for high light exposures that would otherwise saturate the

CCD.

In Free-Running Mode, the default integration time can be

set from 1×to 1/8×frame time via the digital inputs

DIO[11..7] (See Table 14 and Table 25). When changing the

integration time, the user must initiate a Board Reset for the

change to take effect, either by pressing the

BOARD_RESET button (S1) on the Timing Board, or by

setting and resetting the Remote Reset (DIO14) input.

Black Clamp Mode

One of the features of the AD9845A AFE chip is an

optical black clamp. The black clamp (CLPOB) is asserted

during the CCD’s dark pixels and is used to remove residual

offsets in the signal chain, and to track low frequency

variations in the CCD’s black level. The location of these

pulses is fixed in the default KSC−1000 settings, but can be

adjusted dynamically through the 3-wire serial interface.

The default settings are shown in Table 11.

POWER-ON/BOARD RESET INITIALIZATION

When the board is powered up, the Board Reset button is

pressed, or the Remote Rest (DIO14) is toggled, the Altera

PLD is internally reset. When this occurs, state machines in

the PLD will first serially load the initial default values into

the AFE registers, then will load the KSC−1000 frame

tables, line tables, and registers.

Upon completion, the KSC−1000 will be ready to proceed

according to its programmed configuration. In the

background, the Altera PLD monitors the activity of the

3-wire Serial Interface, and monitors and interacts with the

KSC−1000.

AFE Register Default Settings

On power-up or board reset, the AFE registers are

programmed to the default levels shown in Table 9. See the

AD9845A specifications (References) for details of the

AFE registers.

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Table 9. DEFAULT AD9845A AFE REGISTER PROGRAMMING

Address Description Value

(decimal) Notes

0 Operation 128

1VGA Gain

(KAI−2093) 340 Corresponds to a VGA Stage Gain of 9.9 dB

2 Clamp 96 The Output of the AD9845A will be Clamped to Code 96 during the CLPOB Period

3 Control 8 CDS Gain Enabled

4, 5, 6, 7 PXGA Gain 43 Corresponds to a PXGA Stage Gain of 0.0 dB

KSC−1000 Timing Generator Default Settings

On power-up or board reset, The KSC−1000 is

programmed to the default settings as detailed in Table 10

through Table 24. See the KSC−1000 Device Specification

(References) for details of the KSC−1000 registers.

instructs the KSC−1000 to perform the timing sequence

defined in that table. Frame Table 0 is used for Free-Running

Single Channel and Dual Channel modes, and Frame

Table 1 is used for Single Channel 2×2 Binning mode.

The default setting depends on the position of SW2.

Table 10. REGISTER 0 DEFAULT SETTING

Frame Table Address 0 1

The default settings written to Register 1 depend on the

position of SW0 on the Timing Board, used to select

between 1-channel and 2-channel operation.

Table 11. REGISTER 1 DEFAULT SETTING

Pixels Per Line[0..12] 2016 1008

Line Valid Pixel Start[0..12] 9 9

Line Valid Pixel Quadrature Start[0..1] 0 0

Line Valid Pixel End[0..12] 2004 1007

CLPOB1_Pix_Start[0..12] 1982 1000

CLPOB1_Pix_End[0..12] 1992 1004

CLPOB2_Pix_Start[0..12] 0 0

CLPOB2_Pix_End[0..12] 0 0

CLPDM1_Pix_Start[0..12] 6 22

CLPDM1_Pix_End[0..12] 16 30

CLPDM2_Pix_Start[0..12] 0 0

CLPDM2_Pix_End[0..12] 0 0

PBLK_Pix_Start[0..12] 2002 1001

PBLK_Pix_End[0..12] 1 1

RG_Enable 1 1

H6_Enable 0 0

H4_Enable 1 1

H5_ Enable 0 0

SH2_Enable 1 1

SH4_Enable 1 1

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Table 11. REGISTER 1 DEFAULT SETTING (continued)

DATACLK1_Enable 1 1

DATACLK2_Enable 1 1

PIXCLK_Enable 1 1

H3_Enable 1 1

H1_Enable 1 1

H2_Enable 1 1

SH1_Enable 1 1

SH3_Enable 1 1

H6 24 mA Output Enable 0 0

H4 24 mA Output Enable 0 0

H5 24 mA Output Enable 0 0

RG 24 mA Output Enable 0 0

SH2 24 mA Output Enable 0 0

SH4 24 mA Output Enable 0 0

DATACLK1 24 mA Output Enable 0 0

DATACLK2 24 mA Output Enable 0 0

H3 24 mA Output Enable 0 0

H1 24 mA Output Enable 0 0

H2 24 mA Output Enable 0 0

SH1 24 mA Output Enable 0 0

SH3 24 mA Output Enable 0 0

DLL Frequency Range Select 8 8

Operation state of the KSC−1000. The Low Power Mode is

not used on the KAI−2093, so this bit is always LOW.

The Memory Table Mode bit is used to halt execution of the

KSC−1000 timing sequences and to enable programming of

the registers. The KSC−1000 Initialization sequence begins

with setting the Memory Table Mode bit in Register 2 to

Program Mode, and ends by setting the bit to Execution

Mode. See the KSC−1000 Device Specification

(References) for more details.

Table 12. REGISTER 2 SETTINGS

Low Power Enable 0 0

Memory Table Mode 0 1

The default settings written to Register 3 establish the

setup, pulsewidth, and hold timing of the Electronic Shutter

pulse. The Shutter Pulse may occur on a particular line, as

controlled by Register 4, or may be asserted by setting the

“Force INTG_STRT” bit in the Frame Table (Register 8). In

either case, the Electronic Shutter Pulse occurs before the

vertical clocking interval of the Frame Table entry

(Figure 12).

Table 13. REGISTER 3 DEFAULT SETTING

Electronic Shutter Setup Clocks[0..9] 30

Electronic Shutter Pulse Width[0..9] 200

Electronic Shutter Hold Clocks[0..9] 30

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Short integration times may be controlled through use of

the Electronic Shutter. The default setting written to

Shutter will occur. The DIO[11..7] inputs are used to control

the Integration time, by selecting pre-programmed line

numbers, as shown in Table 14.

In Free-Running Mode, the Electronic Shutter pulse

occurs during the previous frame readout. The line number

values are chosen to allow integration times adjustable in

increments of one-eighth the Frame or Flush time.

If the line number is greater than the number of lines

specified in a Frame Table (Register 8), the Electronic

Shutter will not occur. This is the method used to turn the

Shutter off; in this case, the integration time is controlled by

a counter in the Altera PLD (See Table 25).

Table 14. REGISTER 4 DEFAULT SETTING

DIO[11..7] Frame/Flush Integration Free-Running Mode

Integrate Start Pulse Line Number[0..12]

0 1 2040 (Default – No Pulse)

1 1/8 966

2 1/4 828

3 3/8 690

4 1/2 552

5 5/8 414

6 3/4 276

7 7/8 138

> 7 See Table 25 2040 (No Pulse)

The default settings written to Register 5 depend on the

position of SW0 on the Timing Board, used to select

between 1-channel and 2-channel operation.

Table 15. REGISTER 5 DEFAULT SETTING

H6_IDLE_VAL 0 0 (Not Used)

H3_IDLE_VAL 1 1 H1A

H4_IDLE_VAL 0 0 H2A

H1_IDLE_VAL 1 0 H2B

H5_IDLE_VAL 0 0 (Not Used)

H2_IDLE_VAL 0 1 H1B

RG_IDLE_VAL 1 1 RESET

SH2_IDLE_VAL 1 1 SHP1

SH1_IDLE_VAL 1 1 SHP2

SH4_IDLE_VAL 1 1 SHD1

SH3_IDLE_VAL 1 1 SHD2

DATACLK1_IDLE_VAL 1 1 ADCLK (to AFEs)

DATACLK2_IDLE_VAL 0 0 DATACLK (to Framegrabber)

CLPOB_IDLE_VAL 1 1 CLPOB

CLPDM_IDLE_VAL 1 1 CLPDM

AMP_ENABLE_IDLE_VAL 0 0 AMP_ENABLE

FRAME_VALID_IDLE_VAL 0 0 FRAME_VALID

LINE_VALID_IDLE_VAL 0 0 LINE_VALID

INTEGRATE_START_IDLE_VAL 0 0 INTG_START/VES

V1_IDLE_VAL 0 0 V3RD

V2_IDLE_VAL 0 0 (Not Used)

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Table 15. REGISTER 5 DEFAULT SETTING (continued)

V3_IDLE_VAL 0 0 V2

V4_IDLE_VAL 1 1 V1

V5_IDLE_VAL 0 0 (Not Used)

V6_IDLE_VAL 0 0 FDG

The default settings written to Register 6 depend on the

position of SW0 on the Timing Board, used to select

between 1-channel and 2-channel operation.

Table 16. REGISTER 6 DEFAULT SETTING

(1-channel) Data

(2-channel) CCD Signal Name

H6_OFFSET[0..5] 0 0 (Not Used)

H3_OFFSET[0..5] 32 32 H1A

H4_OFFSET[0..5] 29 29 H2A

H1_OFFSET[0..5] 33 31 H2B

H5_OFFSET[0..5] 0 0 (Not Used)

H2_OFFSET[0..5] 31 33 H1B

RG_OFFSET[0..5] 0 0 RESET

SH2_OFFSET[0..5] 31 31 SHP1

SH1_OFFSET[0..5] 31 31 SHP2

SH4_OFFSET[0..5] 63 63 SHD1

SH3_OFFSET[0..5] 63 63 SHD2

DATACLK1_OFFSET[0..5] 42 42 ADCLK (to AFEs)

DATACLK2_OFFSET[0..5] 0 0 DATACLK (to Framegrabber)

The default settings written to Register 7 depend on the

position of SW0 on the Timing Board, used to select

between 1-Channel and 2-Channel operation.

Table 17. REGISTER 7 DEFAULT SETTING

(1-channel) Data

(2-channel) CCD Signal Name

H6_WIDTH[0..4] 16 16 (Not Used)

H3_WIDTH[0..4] 13 13 H1A

H4_WIDTH[0..4] 18 18 H2A

H1_WIDTH[0..4] 13 18 H2B

H5_WIDTH[0..4] 16 16 (Not Used)

H2_WIDTH[0..4] 18 14 H1B

RG_WIDTH[0..4] 8 8 RESET

SH2_WIDTH[0..4] 14 14 SHP1

SH1_WIDTH[0..4] 14 14 SHP2

SH4_WIDTH[0..4] 14 14 SHD1

SH3_WIDTH[0..4] 14 14 SHD2

DATACLK1_WIDTH[0..4] 31 31 ADCLK (to AFEs)

DATACLK2_WIDTH[0..4] 16 16 DATACLK (to Framegrabber)

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