Seiko Epson S1C17153 Manuale utente

Rev. 1.0

CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

S1C17153

Technical Manual

SEIKO EPSON CORPORATION

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko

Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability

of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,

further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical prod-

ucts. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation

or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third

party. When exporting the products or technology described in this material, you should comply with the applicable export control

laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to

export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or

manufacture of weapon of mass destruction or for other military purposes.

All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

Devices

S1 C 17xxx F 00E1

Packing specifications

00 : Besides tape & reel

0A : TCP BL 2 directions

0B : Tape & reel BACK

0C : TCP BR 2 directions

0D : TCP BT 2 directions

0E : TCP BD 2 directions

0F : Tape & reel FRONT

0G: TCP BT 4 directions

0H : TCP BD 4 directions

0J : TCP SL 2 directions

0K : TCP SR 2 directions

0L : Tape & reel LEFT

0M: TCP ST 2 directions

0N : TCP SD 2 directions

0P : TCP ST 4 directions

0Q: TCP SD 4 directions

0R : Tape & reel RIGHT

99 : Specs not fixed

Specification

Package

D: die form; F: QFP, B: BGA, WCSP

Model number

Model name

C: microcomputer, digital products

Product classification

S1: semiconductor

Development tools

S5U1 C 17000 H2 1

Packing specifications

00: standard packing

Version

1: Version 1

Tool type

Hx : ICE

Dx : Evaluation board

Ex : ROM emulation board

Mx: Emulation memory for external ROM

Tx : A socket for mounting

Cx : Compiler package

Sx : Middleware package

Yx : Writer software

Corresponding model number

17xxx: for S1C17xxx

Tool classification

C: microcomputer use

Product classification

S5U1: development tool for semiconductor products

Configuration of product number

CONFIGURATION OF PRODUCT NUMBER

S1C17153 TECHNICAL MANUAL Seiko Epson Corporation i

(Rev. 1.0)

Configuration of product number

CONTENTS

S1C17153 TECHNICAL MANUAL Seiko Epson Corporation i

(Rev. 1.0)

– Contents –

1 Overview........................................................................................................................1-1

1.1 Features ...........................................................................................................................1-1

1.2 Block Diagram..................................................................................................................1-2

1.3 Pads .................................................................................................................................1-3

1.3.1 Pad Configuration Diagram................................................................................1-3

1.3.2 Pin Descriptions.................................................................................................1-5

2 CPU................................................................................................................................2-1

2.1 Features of the S1C17 Core ............................................................................................2-1

2.2 CPU Registers .................................................................................................................2-2

2.3 Instruction Set ..................................................................................................................2-2

2.4 Reading PSR ...................................................................................................................2-5

2.5 Processor Information ......................................................................................................2-6

3 Memory Map, Bus Control ...........................................................................................3-1

3.1 Bus Cycle .........................................................................................................................3-1

3.1.1 Restrictions on Access Size...............................................................................3-2

3.1.2 Restrictions on Instruction Execution Cycles.....................................................3-2

3.2 Internal ROM Area ...........................................................................................................3-2

3.2.1 Embedded ROM ................................................................................................3-2

3.2.2 ROM Read Wait Cycle Setting ..........................................................................3-2

ROMC Read Wait Control Register (ROMC_WAIT) .................................................................. 3-2

3.3 Internal RAM Area............................................................................................................3-3

3.3.1 Embedded RAM ................................................................................................3-3

3.4 Display RAM area ............................................................................................................3-3

3.5 Internal Peripheral Area ...................................................................................................3-3

3.5.1 Internal Peripheral Area 1 (0x4000–).................................................................3-3

3.5.2 Internal Peripheral Area 2 (0x5000–).................................................................3-3

3.6 S1C17 Core I/O Area .......................................................................................................3-4

4 Power Supply ................................................................................................................4-1

4.1 Power Supply Voltage (VDD) .............................................................................................4-1

4.2 Internal Power Supply Circuit...........................................................................................4-1

4.2.1 VD1 Regulator.....................................................................................................4-1

4.2.2 LCD Power Supply Circuit..................................................................................4-1

4.2.3 Heavy Load Protection Mode.............................................................................4-2

4.3 Control Register Details ...................................................................................................4-3

LCD Booster Clock Control Register (LCD_BCLK)................................................................... 4-3

LCD Voltage Regulator Control Register (LCD_VREG) ............................................................ 4-4

VD1 Control Register (VD1_CTL)............................................................................................... 4-5

5 Initial Reset ...................................................................................................................5-1

5.1 Initial Reset Sources ........................................................................................................5-1

5.1.1 #RESET Pin.......................................................................................................5-1

5.1.2 P0 Port Key-Entry Reset ...................................................................................5-1

5.1.3 Resetting by the Watchdog Timer ......................................................................5-1

5.2 Initial Reset Sequence .....................................................................................................5-2

5.3 Initial Settings After an Initial Reset ................................................................................5-2

6 Interrupt Controller (ITC) .............................................................................................6-1

6.1 ITC Module Overview.......................................................................................................6-1

CONTENTS

ii Seiko Epson Corporation S1C17153 TECHNICAL MANUAL

(Rev. 1.0)

6.2 Vector Table......................................................................................................................6-2

Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH).............................. 6-3

6.3 Control of Maskable Interrupts .........................................................................................6-3

6.3.1 Interrupt Control Bits in Peripheral Modules ......................................................6-3

6.3.2 ITC Interrupt Request Processing .....................................................................6-3

6.3.3 Interrupt Processing by the S1C17 Core ...........................................................6-4

6.4 NMI...................................................................................................................................6-4

6.5 Software Interrupts...........................................................................................................6-4

6.6 HALT and SLEEP Mode Cancellation ..............................................................................6-5

6.7 Control Register Details ...................................................................................................6-5

Interrupt Level Setup Register x(ITC_LVx) ............................................................................... 6-5

7 Clock Generator (CLG).................................................................................................7-1

7.1 CLG Module Overview .....................................................................................................7-1

7.2 CLG Input/Output Pins .....................................................................................................7-2

7.3 Oscillators ........................................................................................................................7-2

7.3.1 OSC3B Oscillator...............................................................................................7-2

7.3.2 OSC1A Oscillator...............................................................................................7-3

7.4 System Clock Switching...................................................................................................7-5

7.5 CPU Core Clock (CCLK) Control .....................................................................................7-6

7.6 Peripheral Module Clock (PCLK) Control.........................................................................7-6

7.7 Clock External Output (FOUTA, FOUTB).........................................................................7-7

7.8 Control Register Details ...................................................................................................7-8

Clock Source Select Register (CLG_SRC) ............................................................................... 7-8

Oscillation Control Register (CLG_CTL) ................................................................................... 7-9

FOUTA Control Register (CLG_FOUTA) .................................................................................. 7-10

FOUTB Control Register (CLG_FOUTB) ................................................................................. 7-11

Oscillation Stabilization Wait Control Register (CLG_WAIT) .................................................... 7-11

PCLK Control Register (CLG_PCLK)....................................................................................... 7-12

CCLK Control Register (CLG_CCLK)....................................................................................... 7-13

8 Real-Time Clock (RTC).................................................................................................8-1

8.1 RTC Module Overview .....................................................................................................8-1

8.2 RTC Counters ..................................................................................................................8-1

8.3 RTC Control .....................................................................................................................8-3

8.3.1 Operating Clock Control.....................................................................................8-3

8.3.2 12-hour/24-hour mode selection .......................................................................8-3

8.3.3 RTC Start/Stop ..................................................................................................8-3

8.3.4 Counter Settings ................................................................................................8-3

8.3.5 Counter Read ....................................................................................................8-4

8.4 RTC Interrupts..................................................................................................................8-5

8.5 Control Register Details ...................................................................................................8-5

RTC Control Register (RTC_CTL)............................................................................................. 8-5

RTC Interrupt Enable Register (RTC_IEN)................................................................................ 8-6

RTC Interrupt Flag Register (RTC_IFLG).................................................................................. 8-7

RTC Minute/Second Counter Register (RTC_MS).................................................................... 8-8

RTC Hour Counter Register (RTC_H) ....................................................................................... 8-9

9 I/O Ports (P)...................................................................................................................9-1

9.1 P Module Overview ..........................................................................................................9-1

9.2 Input/Output Pin Function Selection (Port MUX)..............................................................9-2

9.3 Data Input/Output.............................................................................................................9-2

9.4 Pull-up Control .................................................................................................................9-3

9.5 Port Input Interrupt ...........................................................................................................9-3

CONTENTS

S1C17153 TECHNICAL MANUAL Seiko Epson Corporation iii

(Rev. 1.0)

9.6 P0 Port Chattering Filter Function....................................................................................9-4

9.7 P0 Port Key-Entry Reset .................................................................................................9-5

9.8 Control Register Details ...................................................................................................9-5

PxPort Input Data Registers (Px_IN)........................................................................................ 9-5

PxPort Output Data Registers (Px_OUT) ................................................................................. 9-6

PxPort Output Enable Registers (Px_OEN) ............................................................................. 9-6

PxPort Pull-up Control Registers (Px_PU) ............................................................................... 9-6

P0 Port Interrupt Mask Register (P0_IMSK).............................................................................. 9-7

P0 Port Interrupt Edge Select Register (P0_EDGE) ................................................................. 9-7

P0 Port Interrupt Flag Register (P0_IFLG)................................................................................ 9-7

P0 Port Chattering Filter Control Register (P0_CHAT).............................................................. 9-8

P0 Port Key-Entry Reset Configuration Register (P0_KRST) ................................................... 9-9

PxPort Input Enable Registers (Px_IEN).................................................................................. 9-9

P0[3:0] Port Function Select Register (P00_03PMUX) ............................................................ 9-10

P0[7:4] Port Function Select Register (P04_07PMUX) ............................................................ 9-11

P1[3:0] Port Function Select Register (P10_13PMUX) ............................................................ 9-12

10 8-bit Timer (T8)...........................................................................................................10-1

10.1 T8 Module Overview .....................................................................................................10-1

10.2 Count Clock...................................................................................................................10-2

10.3 Count Mode...................................................................................................................10-2

10.4 Reload Data Register and Underflow Cycle..................................................................10-2

10.5 Timer Reset...................................................................................................................10-3

10.6 Timer RUN/STOP Control .............................................................................................10-3

10.7 T8 Output Signals..........................................................................................................10-4

10.8 T8 Interrupts..................................................................................................................10-4

10.9 Control Register Details ................................................................................................10-5

T8 Ch.xCount Clock Select Register (T8_CLKx)..................................................................... 10-5

T8 Ch.xReload Data Register (T8_TRx) ................................................................................. 10-5

T8 Ch.xCounter Data Register (T8_TCx)................................................................................ 10-6

T8 Ch.xControl Register (T8_CTLx)........................................................................................ 10-6

T8 Ch.xInterrupt Control Register (T8_INTx) .......................................................................... 10-7

11 16-bit PWM Timer (T16A2).........................................................................................11-1

11.1 T16A2 Module Overview ...............................................................................................11-1

11.2 T16A2 Input/Output Pins...............................................................................................11-2

11.3 Count Clock...................................................................................................................11-2

11.4 T16A2 Operating Modes ...............................................................................................11-3

11.4.1 Comparator Mode and Capture Mode ............................................................11-4

11.4.2 Repeat Mode and One-Shot Mode.................................................................11-5

11.4.3 Normal Clock Mode and Half Clock Mode......................................................11-5

11.5 Counter Control ............................................................................................................11-6

11.5.1 Counter Reset.................................................................................................11-6

11.5.2 Counter RUN/STOP Control ...........................................................................11-6

11.5.3 Reading Counter Values .................................................................................11-6

11.5.4 Counter Operation and Interrupt Timing Charts..............................................11-7

11.6 Timer Output Control.....................................................................................................11-7

11.7 T16A2 Interrupts............................................................................................................11-9

11.8 Control Register Details ...............................................................................................11-11

T16A Clock Control Register Ch.x(T16A_CLKx).................................................................... 11-11

T16A Counter Ch.xControl Register (T16A_CTLx) ................................................................ 11-12

T16A Counter Ch.xData Register (T16A_TCx) ...................................................................... 11-14

T16A Comparator/Capture Ch.xControl Register (T16A_CCCTLx) ....................................... 11-14

T16A Comparator/Capture Ch.xA Data Register (T16A_CCAx)............................................ 11-16

T16A Comparator/Capture Ch.xB Data Register (T16A_CCBx)............................................ 11-16

CONTENTS

iv Seiko Epson Corporation S1C17153 TECHNICAL MANUAL

(Rev. 1.0)

T16A Comparator/Capture Ch.xInterrupt Enable Register (T16A_IENx) ............................... 11-17

T16A Comparator/Capture Ch.xInterrupt Flag Register (T16A_IFLGx) ................................. 11-18

12 Clock Timer (CT) ........................................................................................................12-1

12.1 CT Module Overview.....................................................................................................12-1

12.2 Operation Clock.............................................................................................................12-1

12.3 Timer Reset...................................................................................................................12-1

12.4 Timer RUN/STOP Control .............................................................................................12-2

12.5 CT Interrupts .................................................................................................................12-2

12.6 Control Register Details ................................................................................................12-3

Clock Timer Control Register (CT_CTL)................................................................................... 12-3

Clock Timer Counter Register (CT_CNT)................................................................................. 12-4

Clock Timer Interrupt Mask Register (CT_IMSK) ..................................................................... 12-4

Clock Timer Interrupt Flag Register (CT_IFLG)........................................................................ 12-4

13 Watchdog Timer (WDT)..............................................................................................13-1

13.1 WDT Module Overview .................................................................................................13-1

13.2 Operation Clock.............................................................................................................13-1

13.3 WDT Control..................................................................................................................13-1

13.3.1 NMI/Reset Mode Selection .............................................................................13-1

13.3.2 WDT Run/Stop Control ...................................................................................13-2

13.3.3 WDT Reset .....................................................................................................13-2

13.3.4 Operations in HALT and SLEEP Modes .........................................................13-2

13.4 Control Register Details ................................................................................................13-2

Watchdog Timer Control Register (WDT_CTL) ........................................................................ 13-2

Watchdog Timer Status Register (WDT_ST)............................................................................ 13-3

14 UART...........................................................................................................................14-1

14.1 UART Module Overview................................................................................................14-1

14.2 UART Input/Output Pins................................................................................................14-2

14.3 Baud Rate Generator ....................................................................................................14-2

14.4 Transfer Data Settings...................................................................................................14-4

14.5 Data Transfer Control ....................................................................................................14-5

14.6 Receive Errors...............................................................................................................14-7

14.7 UART Interrupts ............................................................................................................14-8

14.8 IrDA Interface ................................................................................................................14-9

14.9 Control Register Details ...............................................................................................14-10

UART Ch.xStatus Register (UART_STx)................................................................................ 14-10

UART Ch.xTransmit Data Register (UART_TXDx) ................................................................. 14-12

UART Ch.xReceive Data Register (UART_RXDx) ................................................................. 14-12

UART Ch.xMode Register (UART_MODx) ............................................................................. 14-12

UART Ch.xControl Register (UART_CTLx) ............................................................................ 14-13

UART Ch.xExpansion Register (UART_EXPx) ...................................................................... 14-14

UART Ch.xBaud Rate Register (UART_BRx) ........................................................................ 14-14

UART Ch.xFine Mode Register (UART_FMDx)...................................................................... 14-15

UART Ch.xClock Control Register (UART_CLKx).................................................................. 14-15

15 SPI...............................................................................................................................15-1

15.1 SPI Module Overview....................................................................................................15-1

15.2 SPI Input/Output Pins....................................................................................................15-1

15.3 SPI Clock ......................................................................................................................15-2

15.4 Data Transfer Condition Settings...................................................................................15-2

15.5 Data Transfer Control ....................................................................................................15-3

15.6 SPI Interrupts ................................................................................................................15-5

CONTENTS

S1C17153 TECHNICAL MANUAL Seiko Epson Corporation v

(Rev. 1.0)

15.7 Control Register Details ................................................................................................15-6

SPI Ch.xStatus Register (SPI_STx) ........................................................................................ 15-6

SPI Ch.xTransmit Data Register (SPI_TXDx).......................................................................... 15-7

SPI Ch.xReceive Data Register (SPI_RXDx).......................................................................... 15-7

SPI Ch.xControl Register (SPI_CTLx)..................................................................................... 15-7

16 LCD Driver (LCD).......................................................................................................16-1

16.1 LCD Module Overview ..................................................................................................16-1

16.2 LCD Power Supply ........................................................................................................16-1

16.3 LCD Clock .....................................................................................................................16-2

16.3.1 LCD Operating Clock (LCLK)..........................................................................16-2

16.3.2 Frame Signal...................................................................................................16-3

16.4 Drive Duty Control.........................................................................................................16-3

16.4.1 Drive Duty Switching.......................................................................................16-3

16.4.2 Drive Waveform...............................................................................................16-4

16.5 Display Memory ............................................................................................................16-7

16.6 Display Control..............................................................................................................16-8

16.6.1 Display On/Off.................................................................................................16-8

16.6.2 Inverted Display ..............................................................................................16-8

16.7 LCD Interrupt.................................................................................................................16-9

16.8 Control Register Details ................................................................................................16-9

LCD Timing Clock Select Register (LCD_TCLK)...................................................................... 16-9

LCD Display Control Register (LCD_DCTL)............................................................................ 16-10

LCD Clock Control Register (LCD_CCTL) .............................................................................. 16-11

LCD Voltage Regulator Control Register (LCD_VREG) .......................................................... 16-12

LCD Interrupt Mask Register (LCD_IMSK) ............................................................................. 16-12

LCD Interrupt Flag Register (LCD_IFLG)................................................................................ 16-12

17 Sound Generator (SND) ............................................................................................17-1

17.1 SND Module Overview..................................................................................................17-1

17.2 SND Output Pins...........................................................................................................17-1

17.3 SND Operating Clock....................................................................................................17-1

17.4 Buzzer Frequency and Volume Settings........................................................................17-2

17.4.1 Buzzer Frequency...........................................................................................17-2

17.4.2 Volume level....................................................................................................17-2

17.5 Buzzer Mode and Output Control..................................................................................17-3

17.5.1 Buzzer Mode Selection...................................................................................17-3

17.5.2 Output Control in Normal Mode .....................................................................17-3

17.5.3 Output Control in One-shot Mode ..................................................................17-3

17.5.4 Output Control in Envelope Mode...................................................................17-4

17.6 Control Register Details ...............................................................................................17-5

SND Clock Control Register (SND_CLK)................................................................................. 17-5

SND Control Register (SND_CTL) ........................................................................................... 17-5

Buzzer Frequency Control Register (SND_BZFQ) ................................................................... 17-7

Buzzer Duty Ratio Control Register (SND_BZDT) ................................................................... 17-7

18 Supply Voltage Detection Circuit (SVD)...................................................................18-1

18.1 SVD Module Overview ..................................................................................................18-1

18.2 Comparison Voltage Setting..........................................................................................18-1

18.3 SVD Control ..................................................................................................................18-2

18.4 Control Register Details ................................................................................................18-2

SVD Enable Register (SVD_EN).............................................................................................. 18-2

SVD Comparison Voltage Register (SVD_CMP)...................................................................... 18-3

SVD Detection Result Register (SVD_RSLT)........................................................................... 18-4

CONTENTS

vi Seiko Epson Corporation S1C17153 TECHNICAL MANUAL

(Rev. 1.0)

19 Multiplier/Divider (COPRO).......................................................................................19-1

19.1 Overview .......................................................................................................................19-1

19.2 Operation Mode and Output Mode................................................................................19-1

19.3 Multiplication .................................................................................................................19-2

19.4 Division..........................................................................................................................19-3

19.5 MAC ..............................................................................................................................19-4

19.6 Reading Operation Results ...........................................................................................19-6

20 Electrical Characteristics..........................................................................................20-1

20.1 Absolute Maximum Ratings ..........................................................................................20-1

20.2 Recommended Operating Conditions ...........................................................................20-1

20.3 Current Consumption ....................................................................................................20-1

20.4 Oscillation Characteristics.............................................................................................20-3

20.5 External Clock Input Characteristics .............................................................................20-3

20.6 Input/Output Pin Characteristics ...................................................................................20-3

20.7 SPI Characteristics........................................................................................................20-5

20.8 LCD Driver Characteristics............................................................................................20-5

20.9 SVD Circuit Characteristics...........................................................................................20-8

21 Basic External Connection Diagram........................................................................21-1

22 Evaluation Package ...................................................................................................22-1

Appendix A List of I/O Registers................................................................................ AP-A-1

0x4100–0x4107, 0x506c UART (with IrDA) Ch.0 .................................... AP-A-3

0x4240–0x4248 8-bit Timer Ch.0............................................... AP-A-4

0x4306–0x4314 Interrupt Controller .......................................... AP-A-4

0x4320–0x4326 SPI Ch.0.......................................................... AP-A-4

0x5000–0x5003 Clock Timer ..................................................... AP-A-5

0x5040–0x5041 Watchdog Timer .............................................. AP-A-5

0x5060–0x5081 Clock Generator .............................................. AP-A-5

0x5070–0x5071, 0x50a0–0x50a6 LCD Driver ...................................................... AP-A-6

0x5100–0x5102 SVD Circuit...................................................... AP-A-7

0x5120 Power Generator ............................................. AP-A-8

0x506e, 0x5180–0x5182 Sound Generator............................................. AP-A-8

0x5200–0x52a2 P Port & Port MUX .......................................... AP-A-8

0x5324–0x532c MISC Registers .............................................. AP-A-10

0x5068, 0x5400–0x540c 16-bit PWM Timer Ch.0.................................. AP-A-11

0x54b0 ROM Controller .............................................. AP-A-12

0x56c0–0x56c8 Real-time Clock.............................................. AP-A-12

0xffff84 S1C17 Core I/O.............................................. AP-A-13

Appendix B Power Saving .......................................................................................... AP-B-1

B.1 Clock Control Power Saving......................................................................................... AP-B-1

B.2 Reducing Power Consumption via Power Supply Control ........................................... AP-B-3

Appendix C Mounting Precautions............................................................................ AP-C-1

Appendix D Measures Against Noise........................................................................ AP-D-1

Appendix E Initialization Routine............................................................................... AP-E-1

Appendix F Mask ROM Code Development .............................................................. AP-F-1

Revision History

1 OVERVIEW

S1C17153 TECHNICAL MANUAL Seiko Epson Corporation 1-1

(Rev. 1.0)

Overview1

The S1C17153 is a 16-bit MCU featuring ultra-low-power operations and compact dimensions in die form. The

S1C17153 is ideal for battery-driven electronic equipment, such as OTP cards, eTokens, and remote control units

with a simple display.

Features1.1

The main features of the S1C17153 are listed below.

1.1 FeaturesTable 1.

CPU

CPU core Seiko Epson original 16-bit RISC CPU core S1C17

Multiplier/Divider (COPRO) •16-bit ×16-bit multiplier

•16-bit ×16-bit + 32-bit multiply and accumulation unit

•16-bit ÷16-bit divider

Embedded ROM

Capacity 16K bytes (for both instructions and data)

Embedded RAM

Capacity 2K bytes

Clock generator

System clock source 2 sources (OSC3B/OSC1A)

OSC3B oscillator circuit 2M/1M/500k Hz (typ.) internal oscillator circuit

OSC1A oscillator circuit 32.768 kHz (typ.) crystal oscillator circuit

Other •Core clock frequency control

•Peripheral module clock supply control

LCD driver

Number of driver outputs Segment output: 32 pins

Common output: 4 pins

Other •Includes a power supply voltage booster/reducer.

•Includes a display data memory.

I/O ports

Number of

general-purpose I/O

ports

Max. 12 bits

(Pins are shared with the peripheral I/O.)

Other •Schmitt input

•Pull-up control function

•Port input interrupt: 8 bits

Serial interfaces

SPI 1 channel

UART 1 channel (IrDA1.0 supported)

Timers/Counters

8-bit timer (T8) 1 channel (Generates the SPI clock.)

16-bit PWM timer (T16A2) 1 channel (PWM output, event counter, and count capture functions)

Watchdog timer (WDT) 1 channel (Generates NMI/reset.)

Clock functions

Real-time clock (RTC) 1 channel (Hour, minute, and second counters)

Clock timer (CT) 1 channel (128 Hz to 1 Hz counters)

Sound generator

Buzzer frequency 8 frequencies selectable

Volume control 8 steps adjustable

Other •One-shot buzzer

•Auto envelope function

Analog circuits

Supply voltage

detection circuit

(SVD) 1 channel (Detection voltage: 13 levels)

Interrupts

Reset interrupt #RESET pin/watchdog timer

NMI Watchdog timer

Programmable interrupts 8 systems (8 levels)

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