Teridian 73S8024C Manuale utente

Simplifying System Integration

73S8024C

Demo Board User Manual

November 11, 2009

Rev. 1.3

UM_8024C_061

73S8024C Demo Board User Manual UM_8024C_061

2 Rev. 1.3

Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.

Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.

All other trademarks are the property of their respective owners.

Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly

contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms

and Conditions. The company assumes no responsibility for any errors which may appear in this

document, reserves the right to change devices or specifications detailed herein at any time without

notice and does not make any commitment to update the information contained herein. Accordingly, the

reader is cautioned to verify that this document is current by comparing it to the latest version on

http://www.teridian.com or by checking with your sales representative.

Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618

TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com

UM_8024C_061 73S8024C Demo Board User Manual

Rev. 1.3 3

Table of Contents

1Introduction ...................................................................................................................................5

1.1 Package Contents....................................................................................................................5

1.2 Safety and ESD Notes.............................................................................................................5

2Basic Connections ........................................................................................................................6

3Hardware Description....................................................................................................................7

3.1 Demo Board Connectors, Jumpers and Test Points .................................................................7

3.2 Recommended Operating Conditions and Absolute Maximum Ratings.....................................9

3.373S8024C Pin Description.......................................................................................................9

3.4 73S8024C Pinout..................................................................................................................11

4Design Considerations................................................................................................................12

4.1 General Layout Rules ............................................................................................................12

4.2 Optimization for Compliance with EMV and NDS....................................................................12

573S8024C Demo Board Schematics, PCB Layouts and Bill of Materials..................................13

5.1 Schematic..............................................................................................................................13

5.2 Bill of Materials ......................................................................................................................14

5.3 PCB Layouts..........................................................................................................................15

6Ordering Information...................................................................................................................18

7Related Documentation...............................................................................................................18

8Contact Information.....................................................................................................................18

Revision History..................................................................................................................................19

73S8024C Demo Board User Manual UM_8024C_061

4 Rev. 1.3

Figures

Figure 1: 73S8024C Demo Board............................................................................................................5

Figure 2: 73S8024C Demo Board Basic Connections..............................................................................6

Figure 3: 73S8024C Demo Board Connectors, Jumpers and Test Points.................................................8

Figure 4: 73S8024C SO28 Pinout (Top View)........................................................................................11

Figure 5: 73S8024C Demo Board Electrical Schematic..........................................................................13

Figure 6: 73S8024C Demo Board Top View...........................................................................................15

Figure 7: 73S8024C Demo Board Bottom View......................................................................................15

Figure 8: 73S8024C Demo Board Top Signal Layer...............................................................................16

Figure 9: 73S8024C Demo Board Middle Layer 1, Ground Plane...........................................................16

Figure 10: 73S8024C Middle Layer 2, Supply Plane ..............................................................................17

Figure 11: 73S8024C Demo Board Bottom Signal Layer........................................................................17

Tables

Table 1: 73S8024C Demo Board Connector, Jumper and Test Points......................................................7

Table 2: Recommended Operating Conditions.........................................................................................9

Table 3: Absolute Maximum Ratings........................................................................................................9

Table 4: 73S8024C Card Interface Pins...................................................................................................9

Table 5: 73S8024C Miscellaneous Pins.................................................................................................10

Table 6: 73S8024C Power and Ground Pins..........................................................................................10

Table 7: 72S8024C Microcontroller Interface Pins..................................................................................10

Table 8: 73S8024C Demo Board Bill of Materials...................................................................................14

Table 9: Order Numbers and Packaging Marks......................................................................................18

UM_8024C_061 73S8024C Demo Board User Manual

Rev. 1.3 5

1 Introduction

The 73S8024C Demo Board is a platform for evaluating the Teridian 73S8024C Smart Card Interface

device. The board incorporates the 73S8024C integrated circuit and has been designed to operate either

as a standalone platform (to be used in conjunction with an external microcontroller) or as a daughter

card to be used in conjunction with the 73S1121F evaluation platform.

The board has been designed to comply with the EMV 2000 Specification, Version 4.0. 73S8024C Demo

Boards can easily be modified to comply with NDS specifications by replacing a few external components

that are highlighted in this document.

Figure 1: 73S8024C Demo Board

1.1 Package Contents

The 73S8024C Demo Board Kit includes:

•A 73S8024C Demo Board

•The following documents on CD:

•73S8024C Data Sheet

•73S8024C Demo Board User Manual (this document)

•Application Note

1.2 Safety and ESD Notes

Extreme caution should be taken when handling the 73S8024C Demo Board after

connection to live voltages!

The 73S8024C Demo Board is ESD sensitive! ESD precautions should be taken when

handling this board!

73S8024C Demo Board User Manual UM_8024C_061

6 Rev. 1.3

2 Basic Connections

The basic connections to the demo board are described below and shown in Figure 2.

1. Connect power supply: Apply 3.3 V to pin 10 of J4.

2. Control signals to the device can be connected through J2 and J4 (see Figure 2 and the Electrical

Schematic, Figure 5).

3. To set the clock frequency with an external clock source:

•Set JP1 to the SCLK setting.

•Apply clock source to pin 1 of J2.

•Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins to set the desired clock rate as follows:

CLKDIV1 = CLKDIV2 = 0 clock frequency = SCLK/8

CLKDIV1 = 0, CLKDIV2 =1 clock frequency = SCLK/4

CLKDIV1 = 1, CLKDIV2 =0 clock frequency = SCLK

CLKDIV1 = CLKDIV2 = 1 clock frequency = SCLK/2

4. To set the clock frequency using crystal Y1:

•The crystal included on the demo board is 12 MHz.

•Set JP1 to XTAL position.

•Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins to set the desired clock rate as follows:

CLKDIV1 = CLKDIV2 = 0 clock frequency = 1.5 MHz

CLKDIV1 = 0, CLKDIV2 =1 clock frequency = 3 MHz

CLKDIV1 = 1, CLKDIV2 =0 clock frequency = 12 MHz

CLKDIV1 = CLKDIV2 = 1 clock frequency = 6 MHz

Figure 2: 73S8024C Demo Board Basic Connections

CKDIV2

CKDIV1

RSTIN

CMDVCC

GND

VDD

PWRDN

5V/#V

GND

SCLK

OFF

I/OUC

AUX1UC

AUX2UC

External clock source. JP1 must be in

position SCLK when using an

external clock. Otherwise, pin SCLK

can be left open.

Power

Supply:

Configure JP2

to 3.3V

Power Supply:

+2.7V to +3.6V

(3.3V Typ.) / 50mA

Note: CLKSTOP and CLKLEV

can be left NC if unused.

5V/#V too, for 5V cards only.

UM_8024C_061 73S8024C Demo Board User Manual

Rev. 1.3 7

3 Hardware Description

3.1 Demo Board Connectors, Jumpers and Test Points

Table 1 describes the73S8024C Demo Board connectors, jumpers and test points. The Item # in Table 1

refers to Figure 3.

Table 1: 73S8024C Demo Board Connector, Jumper and Test Points

Item

Schematic/

Silkscreen

Reference Name Function

Connectors:

1 J2 5V Board Supply /

Auxiliary Interface 73S8024C auxiliary interface (I/OUC, AUX1UC,

AUX2UC), external clock (SCLK) and interrupt (OFF)

pins. The external clock (SCLK) can be left open when

JP1 is in position XTAL.

The 5V power supply is unused and must be left open

and JP2 must be inserted in position 3.3V.

9 J4 3.3V Board Power /

Digital Control

Signals

3.3V board power supply and the 73S8024C host

control signals RSTIN, CMDVCC, 5V/#V, PWRDWN,

CLKDIV2 and CLKDIV1.

16 J5 Smart Card

Connector Smart card connector.

When inserting a card (credit card size format), contacts

must face up.

11 J6 Smart Card

Connector SIM/SAM smart card format connector.

J6 is wired in parallel to the smart card connector J5

(underneath the PCB). No SIM/SAM should be inserted

when using the credit-card size connector J5.

Jumpers:

3 JP1 Clock Selection Jumper to select between a crystal or an external clock

as the frequency reference to the device. The default

setting is for a crystal.

17 JP2 VPC Select Jumper to select the value of the power supply for the

smart card DC-DC converter (73S8024C input VPC).

To support both card voltages, JP2 must be set to

position 3.3V. The default setting is 3.3V.

2 JP3 VDD Select Jumper to select the digital voltage which supplies the

73S8024C. Must be set for 3.3V.

8 JP4 – Not used.

14 JP5

JP6 Card Polarity

Detect Select The setting of JP5 and JP6 depends on the type of

smart card connector used (nominally open or closed)

and which 73S8024C card presence switch input is

used. The switch is nominally open for the 73S8024C

Demo Board. The jumpers can be set to:

1. Use of PRES (default): JP5 set to PRES; JP6 set

to VDD.

2. Use of PRES: JP5 set to PREB; JP6 set to GND.

73S8024C Demo Board User Manual UM_8024C_061

8 Rev. 1.3

Item

Schematic/

Silkscreen

Reference Name Function

Test Points:

10 TP1 Pin 17 (VDDF_ADJ) VDD voltage fault adjustment. The pin to the left is

connected to the VDDF_ADJ pin of the 73S8024C and

the pin to the right is GND. When either a resistor R3,

or a resistor network R1 and R3 is populated on the

board, it adjusts the VDD fault level that internally

triggers a card deactivation sequence.

By default, the resistors R1 and R3 are not connected.

This provides a VDD fault level of 2.3V typical (internally

set to the 73S8024C). Refer to the 73S8024C Data

Sheet for further information about VDD fault level and

determination of the resistor values.

20 TP2 Factory Test Factory test pin. Do not connect.

TP3

TP4

TP5

TP6

TP7

TP8

VCC

I/O

RST

CLK

2-pin test points for each respective smart card signal.

The pin label name is the respective signal (i.e. VCC,

CLK) and the 2nd pin is GND.

Figure 3: 73S8024C Demo Board Connectors, Jumpers and Test Points

UM_8024C_061 73S8024C Demo Board User Manual

Rev. 1.3 9

3.2 Recommended Operating Conditions and Absolute Maximum Ratings

Table 2 lists the recommended operating conditions and Table 3 lists the absolute maximum ratings.

Operation outside these rating limits may cause permanent damage to the device.

Table 2: Recommended Operating Conditions

Parameter Rating

Supply Voltage VDD 2.7 to 3.6 VDC

Supply Voltage VPC 2.7 to 3.6 VDC

Ambient Operating Temperature -40 °C to +85 °C

Input Voltage for Digital Inputs 0 V to VDD + 0.3 V

Table 3: Absolute Maximum Ratings

Parameter

Rating

Supply Voltage VDD -0.5 to 4.0 VDC

Supply Voltage VPC -0.5 to 4.0 VDC

Input Voltage for Digital Inputs -0.3 to (VDD+0.5) VDC

Storage Temperature -60 °C to 150 °C

Pin Voltage -0.3 to (VDD+0.5) VDC

Pin Current ±100 mA

ESD Tolerance – Card interface pins +/- 6 kV

ESD Tolerance – Other pins +/- 2 kV

ESD testing on Card pins is HBM condition, 3 pulses, each polarity referenced to ground.

3.3 73S8024C Pin Description

Table 4: 73S8024C Card Interface Pins

Name

Pin #

Description

I/O 11 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC.

AUX1 13 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.

AUX2 12 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.

RST 14 Card reset: provides reset (RST) signal to card.

CLK 15 Card clock: provides clock signal (CLK) to card. The rate of this clock is

determined by crystal oscillator frequency or external clock input and

CLKDIV selections.

PRES 10 Card Presence switch: active high indicates card is present. Should be tied

to GND when not used, but it includes a high-impedance pull-down resistor.

PRES 9 Card Presence switch: active low indicates card is present. Should be tied

to VDD when not used, but it includes a high-impedance pull-up resistor.

VCC 17 Card power supply: logically controlled by sequencer output of LDO

regulator. Requires an external filter capacitor to the card GND.

GND 14 Card ground.

73S8024C Demo Board User Manual UM_8024C_061

10 Rev. 1.3

Table 5: 73S8024C Miscellaneous Pins

Name Pin # Description

XTALIN 24 Crystal oscillator input: can either be connected to crystal or driven as a

source for the card clock.

XTALOUT 25 Crystal oscillator output: connected to crystal. Left open if XTALIN is being

used as external clock input.

VDDF_ADJ 18 VDD fault threshold adjustment input: this pin can be used to adjust the VDDF

values (controls deactivation of the card). Must be left open if unused.

NC 5,7 Non-connected pin.

Table 6: 73S8024C Power and Ground Pins

Name

Pin #

Description

VDD 21 System interface supply voltage and supply voltage for internal circuitry.

VPC 6 DC-DC converter power supply source.

GND 4 DC-DC converter ground.

GND 22 Digital ground.

LIN 5 External inductor. Connect external inductor from pin 2 to VPC. Keep the

inductor close to pin 2.

Table 7: 72S8024C Microcontroller Interface Pins

Name Pin # Description

CMDVCC

Command VCC (negative assertion): Logic low on this pin causes the LDO

regulator to ramp the VCC supply to the card and initiates a card activation

sequence, if a card is present.

5V/#V 3 5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card

interface, logic low selects 3 volt operation.

When the part is to be used with

a single card voltage, this pin should be tied to either GND or VDD. However,

it includes a high impedance pull-up resistor to default this pin high

(selection of 5V card) when not connected.

PWRDN 8 Power Down control input. Active high. When the Power Down mode is set

high, all internal analog functions are disabled to place the 73S8024C in its

lowest power consumption mode. The Power Down mode is only allowed

out of a card session (i.e. when CMDVCC = 1)

CLKDIV1

CLKDIV2

2 Sets the divide ratio from the XTAL oscillator (or external clock input) to the

card clock. These pins include pull-down resistors.

CLKDIV1

CLKDIV2

CLOCK RATE

0 0 XTALIN/8

XTALIN/4

XTALIN/2

1 0 XTALIN

OFF 23 Interrupt signal to the processor. Active low - multi-function indicating fault

conditions and/or card presence. Open drain output configuration; includes

an internal 22 kΩ pull-up to VDD.

RSTIN 20 Reset Input: This signal is the reset command to the card.

I/OUC 26 System controller data I/O to/from the card. Includes a pull-up resistor to VDD.

AUX1UC 27 System controller auxiliary data I/O to/from the card. Includes a pull-up

resistor to VDD.

AUX2UC 28 System controller auxiliary data I/O to/from the card. Includes a pull-up

resistor to VDD.

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