Tews Technologies TIP255 Manuale utente

The Embedded I/O Company

TIP255

2 Mbytes SRAM Memory

with Battery Backup

Version 1.0 Revision C

User Manual

Issue 1.0.6

September 2009

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7 25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19

e-mail: [email protected] www.tews.com

TIP255 User Manual Issue 1.0.6 Page 2 of 13

TIP255-10

2 Mbytes SRAM memory with battery backup

TIP255-10-ET

2 MB of SRAM Memory with battery backup,

operating temperature -40°C to +85°C

This document contains information, which is

proprietary to TEWS TECHNOLOGIES GmbH. Any

reproduction without written permission is forbidden.

TEWS TECHNOLOGIES GmbH has made any

effort to ensure that this manual is accurate and

complete. However TEWS TECHNOLOGIES GmbH

reserves the right to change the product described

in this document at any time without notice.

TEWS TECHNOLOGIES GmbH is not liable for any

damage arising out of the application or use of the

device described herein.

Style Conventions

Hexadecimal characters are specified with prefix 0x,

i.e. 0x029E (that means hexadecimal value 029E).

For signals on hardware products, an ‚Active Low’ is

represented by the signal name with # following, i.e.

IP_RESET#.

Access terms are described as:

W Write Only

R Read Only

R/W Read/Write

R/C Read/Clear

R/S Read/Set

All trademarks mentioned are property of their respective owners.

TIP255 User Manual Issue 1.0.6 Page 3 of 13

Issue Description Date

1.0 First Issue February 2002

1.1 New Module Revision B March 2002

1.2 New Module Revision C October 2003

1.3 Added Security Warning (Lithium Battery) August 2004

1.4 New Module Version TIP255-10-ET April 2005

1.5 New address TEWS LLC September 2006

1.0.6 New User Manual Issue Notation September 2009

TIP255 User Manual Issue 1.0.6 Page 4 of 13

Table of Contents

1PRODUCT DESCRIPTION.........................................................................................6

2TECHNICAL SPECIFICATION...................................................................................7

3ID PROM CONTENTS................................................................................................8

4IP ADDRESSING........................................................................................................9

4.1 I/O Addressing.................................................................................................................................9

4.1.1 SRAM Control Register (CR)................................................................................................9

4.1.2 SRAM Status Register (SR).................................................................................................9

4.1.3 Interrupt Vector Register (INTVEC)....................................................................................10

4.2 Memory Addressing......................................................................................................................10

5MODULE INSTALLATION .......................................................................................11

5.1 Security Warning (Lithium Battery).............................................................................................11

5.2 Jumper Configuration...................................................................................................................12

5.2.1 Jumper Settings..................................................................................................................12

6PIN ASSIGNMENT ...................................................................................................13

TIP255 User Manual Issue 1.0.6 Page 5 of 13

List of Figures

FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6

FIGURE 5-1 : JUMPER CONFIGURATION....................................................................................................12

List of Tables

TABLE 2-1 : TECHNICAL SPECIFICATION.....................................................................................................7

TABLE 3-1 : ID PROM CONTENTS..................................................................................................................8

TABLE 4-1 : REGISTER SET............................................................................................................................9

TABLE 4-2 : SRAM CONTROL REGISTER (CR).............................................................................................9

TABLE 4-3 : SRAM STATUS REGISTER (SR) ................................................................................................9

TABLE 6-1 : PIN ASSIGNMENT J1................................................................................................................13

TIP255 User Manual Issue 1.0.6 Page 6 of 13

1 Product Description

The TIP255 is an IndustryPack®compatible module that offers an easy and reliable way to implement

2 Mbytes of SRAM memory with battery backup.

The 2 Mbyte SRAM is organized in two banks, each bank is providing 512k x 16 bit memory. For all

SRAM devices battery backup is provided by an on board lithium cell. During normal operation

(standard 5V supply applied to the SRAM’s) the capacity of the lithium cell is monitored every 24

hours by the battery monitor device. In addition an interrupt is generated if the battery voltage is too

low. The battery monitor device switches the power supply of the SRAM’s from the standard 5V to the

battery if the 5V drop below the threshold level of the battery monitor device. At this point any active

access to the SRAM’s is executed correctly within 1.5 µs. After this time further accesses to the

SRAM’s are not possible.

Accesses to the TIP255 SRAM memory occur within the IP memory space. The IP I/O space holds the

Interrupt Control Register, the Interrupt and Battery Status Register and the Interrupt Vector Register.

Industry Pack I/O Interface

Pack logic InterfaceIndustry

ID-PROM

4MbitSRAM

(512 Kbyte)

Local

Control

Logic

Bank1

1 Mbyte SRAM

16 bit wide

Bank2

Local +3.3V

1 Mbyte SRAM

16 bit wide

4 Mbit SRAM

(512 Kbyte)

4 Mbit SRAM

(512 Kbyte)

4 Mbit SRAM

(512 Kbyte)

Nonvolatile

SRAM Controller

Battery

Figure 1-1 : Block Diagram

CAUTION! - This system contains a lithium battery. Lithium batteries may explode if

mishandled.

Please refer to chapter “Security Warning (Lithium Battery)”.

TIP255 User Manual Issue 1.0.6 Page 7 of 13

2 Technical Specification

IP Interface Single Size IndustryPack®Logic Interface

ID PROM supports auto-configuration

Module Specific Data

Memory Size 2 Mbytes SRAM Memory

Memory Organization 2 banks of 1 Mbyte

Data Width 16 bit

Wait States No wait states

Interrupts IntReq0 on battery low

SRAM

CMOS SRAM Chip 4 x 512x8 low-low power SRAM

Battery

On Board Battery Type CR2430 Lithium Cell (285mAh capacity)

Battery Fault Voltage 2.6V typical

Battery Lifetime (caused by

self discharching effects) @+25°C : approx. 8 years

@+45°C : approx. 4 years

Battery Current in

Memory Backup Mode 4µA typical @ +25°C

Min. Data Retention Voltage 2.0V

5V Power Failure Threshold 4.37V typical

I/O Interface No connections to IP I/O connector

Physical Data

Power Requirements 65mA typical @ + 5V DC

Temperature Range Operating

Storage

0 °C to +70 °C

-40°C to +85°C (TIP255-10-ET)

-55 °C to +125 °C

MTBF 550000 h

Humidity 5 – 95 % non-condensing

Table 2-1 : Technical Specification

TIP255 User Manual Issue 1.0.6 Page 8 of 13

3 ID PROM Contents

ADDRESS FUNCTION CONTENTS

0x01 ASCII ‘I’ 49

0x03 ASCII ‘P’ 50

0x05 ASCII ‘A’ 41

0x07 ASCII ‘C’ 43

0x09 Manufacturer ID B3

0x0B Model Number 31

0x0D Revision 10

0x0F RESERVED 00

0x11 Driver-ID Low – Byte 00

0x13 Driver-ID High – Byte 00

0x15 Number of bytes used 0C

0x17 Check Sum 9C

Table 3-1 : ID PROM Contents

TIP255 User Manual Issue 1.0.6 Page 9 of 13

4 IP Addressing

4.1I/O Addressing

The complete register set of the TIP255-10 is accessible in the I/O space of the IP.

Address Symbol Description Size (Bit) Access

0x01 CR Interrupt Control Register 8 R/W

0x03 SR Interrupt and Battery Status Register 8 R/W

0x05 INTVEC Interrupt Vector Register 8 R/W

Table 4-1 : Register Set

4.1.1 SRAM Control Register (CR)

The CR is a read/write register to enable interrupt generation of the TIP255.

Bit Symbol Description Access

7:1 N/A

0 INT

ENA Interrupt Enable

1 = an interrupt is always initiated, whenever the battery

voltage falls below the reference voltage of the

nonvolatile SRAM controller (Vref=2.6V typical).

R/W

Table 4-2 : SRAM Control Register (CR)

4.1.2 SRAM Status Register (SR)

The SR is a read/write register to observe battery and interrupt status of the TIP255.

Bit Symbol Description Access

7:2 N/A

1 IS Interrupt Status

1 = if an interrupt is pending. This bit is reset to ‘0’ by a write

access to this register with any data.

R/W

0 BS Battery Status

1 = the battery voltage has fallen below the reference voltage

of Vref=2.6V typical. In this case the battery will soon

reach end-of-live. For reliable function of the battery

backup, the battery should be replaced.

R/W

Table 4-3 : SRAM Status Register (SR)

TIP255 User Manual Issue 1.0.6 Page 10 of 13

4.1.3 Interrupt Vector Register (INTVEC)

The INTVEC is a read/write register. It must be loaded by software with the desired interrupt vector

value, when interrupts shall be used.

A reset will set the INTVEC to the default value of 0x00.

4.2Memory Addressing

Access to the TIP255 SRAM is simply done by reading or writing data to the address space where the

TIP255 memory is mapped in the processors memory space. 8 bit and 16 bit accesses are supported.

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