Texas Instruments DAC63202W Manuale utente

DAC63202W 12-Bit, Dual, Voltage and Current Output Smart DACs

WithAuto‑Detected I2C, SPI, or PMBus™ Interface in DSBGA

1 Features

• Programmable voltage or current outputs with

flexible configuration:

– Voltage outputs:

• 1 LSB DNL

• Gains of 1 ×, 1.5 ×, 2 ×, 3 ×, and 4 ×

– Current outputs:

• 1 LSB INL and DNL (8-bit)

• ±25 μA, ±50 μA, ±125 μA, ±250 μA output-

range options

• Programmable comparator mode for all channels

• High-impedance output when VDD is off

• High-impedance and resistive pulldown power-

down modes

• 50-MHz SPI-compatible interface

• Automatically detects I2C, SPI, or PMBus™

interface

– 1.62-V VIH with VDD = 5.5 V

• General-purpose input/output (GPIO) configurable

as multiple functions

• Predefined waveform generation: sine, cosine,

triangular, sawtooth

• User-programmable nonvolatile memory (NVM)

• Internal, external, or power-supply as reference

• Wide operating range:

– Power supply: 1.8 V to 5.5 V

– Temperature: –40˚C to +125˚C

• Tiny package:

– 16-pin DSBGA: 1.72 mm × 1.72 mm, nominal

2 Applications

•Optical module

•High performance computing

•Standard notebook PC

3 Description

The DAC63202W is a 12-bit, dual-channel, buffered,

voltage-output and current-output smart digital-to-

analog converter (DAC). The DAC63202W devices

support Hi-Z power-down mode and Hi-Z output

during power-off conditions. The DAC outputs provide

a force-sense option for use as a programmable

comparator and current sink. The multifunction GPIO,

function generation, and programmable nonvolatile

memory (NVM) enable these smart DACs for

processor-less applications and design reuse. This

device automatically detects I2C, SPI and PMBus

interfaces, and contain an internal reference.

The feature set combined with the tiny package

and low power make this smart DAC an excellent

choice for applications such as voltage margining and

scaling, dc set-point for biasing and calibration, and

waveform generation.

Package Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM)

DAC63202W YBH (DSBGA, 16) 1.72 mm × 1.72 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

SMPS / LDO R1

VFB

SENSE

GND

VOUT

BOOT

DAC63202W

VDD

VIN

VOUT/

IOUT

VOUT/

IOUT

DAC

REG

DAC

BUF

DAC

REG

DAC

BUF

NVM

Internal

Reference

LDO

Output Configuration

Logic

VREF CAP

AGND

Digital Interface

SCL/SYNC

SDA/SCLK

A0/SDI

PROTECT

1.5 μ

0.1 μ



10 kΩ

Power-supply: 0

Power-supply: 1

Voltage Margining and Scaling Using the DAC63202W

DAC63202W

SLASF73 – APRIL 2023

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................4

6.5 Electrical Characteristics: Voltage Output...................5

6.6 Electrical Characteristics: Current Output...................7

6.7 Electrical Characteristics: Comparator Mode..............8

6.8 Electrical Characteristics: General..............................9

6.9 Timing Requirements: I2C Standard Mode............... 10

6.10 Timing Requirements: I2C Fast Mode.....................10

6.11 Timing Requirements: I2C Fast Mode Plus............. 10

6.12 Timing Requirements: SPI Write Operation............ 11

6.13 Timing Requirements: SPI Read and Daisy

Chain Operation (FSDO = 0).......................................11

6.14 Timing Requirements: SPI Read and Daisy

Chain Operation (FSDO = 1).......................................11

6.15 Timing Requirements: GPIO...................................12

6.16 Timing Diagrams.....................................................12

6.17 Typical Characteristics: Voltage Output.................. 14

6.18 Typical Characteristics: Current Output.................. 19

6.19 Typical Characteristics: Comparator.......................23

6.20 Typical Characteristics: General............................. 24

7 Detailed Description......................................................25

7.1 Overview...................................................................25

7.2 Functional Block Diagram.........................................25

7.3 Feature Description...................................................26

7.4 Device Functional Modes..........................................27

7.5 Programming............................................................ 45

7.6 Register Map.............................................................53

8 Application and Implementation..................................71

8.1 Application Information............................................. 71

8.2 Typical Application.................................................... 71

8.3 Power Supply Recommendations.............................73

8.4 Layout....................................................................... 73

9 Device and Documentation Support............................75

9.1 Documentation Support............................................ 75

9.2 Receiving Notification of Documentation Updates....75

9.3 Support Resources................................................... 75

9.4 Trademarks...............................................................75

9.5 Electrostatic Discharge Caution................................75

9.6 Glossary....................................................................75

10 Mechanical, Packaging, and Orderable

Information.................................................................... 75

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

April 2023 * Initial Release

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5 Pin Configuration and Functions

1 2 3 4

Not to scale

VREF OUT0 NC GPIO/SDO

VDD FB0 NC SCL/SYNC

AGND FB1 NC A0/SDI

CAP OUT1 NC SDA/SCLK

Figure 5-1. YBH (16-pin DSBGA) Package, Top View

Table 5-1. Pin Functions

PIN TYPE DESCRIPTION

NO. NAME

A1 VREF Power

External reference input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND.

Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up before VDD. In

case an external reference is used, make sure the reference ramps up after VDD.

A2 OUT0 Output Analog output voltage from DAC channel 0.

A3 NC NC Not connected.

A4 GPIO/SDO Input/Output

General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS. For STATUS and

SDO, connect the pin to the IO voltage with an external pullup resistor. If unused, connect the GPIO pin to VDD or

AGND using an external resistor. This pin can ramp up before VDD.

B1 VDD Power Supply voltage.

B2 FB0 Input Voltage feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier output. In

current-output mode, keep this pin unconnected to minimize leakage current.

B3 NC NC Not connected.

B4 SCL/SYNC Output I2C serial interface clock or SPI chip select input. This pin must be connected to the IO voltage using an external

pullup resistor. This pin can ramp up before VDD.

C1 AGND Ground Ground reference point for all circuitry on the device.

C2 FB1 Input Voltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier output. In

current-output mode, keep this pin unconnected to minimize leakage current.

C3 NC NC Not connected.

C4 A0/SDI Input

Address configuration pin for I2C or serial data input for SPI.

For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (Section 7.5.2.2.1).

For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD.

D1 CAP Power External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and

AGND.

D2 OUT1 Output Analog output voltage from DAC channel 01

D3 NC NC Not connected.

D4 SDA/SCLK Input/Output Bidirectional I2C serial data bus or SPI clock input. This pin must be connected to the IO voltage using an external

pullup resistor in the I2C mode. This pin can ramp up before VDD.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VDD Supply voltage, VDD to AGND –0.3 6 V

Digital inputs to AGND –0.3 VDD + 0.3 V

VFBX to AGND –0.3 VDD + 0.3 V

VOUTX to AGND –0.3 VDD + 0.3 V

VREF External reference, VREF to AGND –0.3 VDD + 0.3 V

Current into any pin except the OUTx, VDD, and AGND pins –10 10 mA

TJJunction temperature –40 150 °C

Tstg Storage temperature –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins((2)) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VDD Positive supply voltage to ground (AGND) 1.7 5.5 V

VREF External reference to ground (AGND) 1.7 VDD V

VIH Digital input high voltage, 1.7 V < VDD ≤ 5.5 V 1.62 V

VIL Digital input low voltage 0.4 V

CCAP External capacitor on CAP pin 0.5 15 μF

TAAmbient temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1)

DAC63202W

UNITYBH (DSBGA)

16 PINS

RθJA Junction-to-ambient thermal resistance 80.2 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 0.4 °C/W

RθJB Junction-to-board thermal resistance 18.8 °C/W

ΨJT Junction-to-top characterization parameter 0.2 °C/W

ΨJB Junction-to-board characterization parameter 18.8 °C/W

(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

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6.5 Electrical Characteristics: Voltage Output

all minimum/maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,

DAC reference tied to VDD, gain = 1 ×, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive

load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STATIC PERFORMANCE

Resolution 12 Bits

INL Integral nonlinearity((1)) –5 5 LSB

DNL Differential nonlinearity(1) –1 1 LSB

Zero-code error(4)

Code 0d into DAC, external reference, VDD = 5.5 V 6 12

Code 0d into DAC, internal VREF, gain = 4 ×,

VDD = 5.5 V 6 15

Zero-code error temperature

coefficient(4) ±10 µV/°C

Offset error(4) (6)

1.7 V ≤ VDD < 2.7 V, VFB pin shorted to VOUT, DAC

code: 32d –0.75 0.3 0.75

%FSR

2.7 V ≤ VDD ≤ 5.5 V, VFB pin shorted to VOUT,

DAC code: 32d –0.5 0.25 0.5

Offset-error temperature

coefficient(4) VFB pin shorted to VOUT, DAC code: 32d ±0.0003 %FSR/°C

Gain error(4) Between end-point codes: 32d to 4064d –0.5 0.25 0.5 %FSR

Gain-error temperature

coefficient(4) Between end-point codes: 32d to 4064d ±0.0008 %FSR/°C

Full-scale error(4) (6) 1.7 V ≤ VDD < 2.7 V, DAC at full-scale –1 1 %FSR

2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale –0.5 0.5

Full-scale-error temperature

coefficient(4) DAC at full-scale ±0.0008 %FSR/°C

OUTPUT

Output voltage Reference tied to VDD 0 VDD V

CLCapacitive load(2) RL = infinite, phase margin = 30° 200 pF

Phase margin = 30° 1000

Short-circuit current

VDD = 1.7 V, full-scale output shorted to AGND or

zero-scale output shorted to VDD 15

VDD = 2.7 V, full-scale output shorted to AGND or

zero-scale output shorted to VDD 50

VDD = 5.5 V, full-scale output shorted to AGND or

zero-scale output shorted to VDD 60

Output-voltage headroom(2)

To VDD (DAC output unloaded, internal reference =

1.21 V), VDD ≥ 1.21 V × gain + 0.2 V 0.2 V

To VDD and to AGND

(DAC output unloaded, external reference at VDD (gain

= 1 ×), the VREF pin is not shorted to VDD)

0.8

%FSR

To VDD and to AGND (ILOAD = 10 mA at VDD = 5.5 V,

ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD =

1.8 V), external reference at VDD (gain = 1 ×), the VREF

pin is not shorted to VDD)

ZOVFB dc output impedance(3)

DAC output enabled, internal reference (gain = 1.5 ×

or 2 ×) or external reference at VDD (gain = 1 ×), the

VREF pin is not shorted to VDD

400 500 600 kΩ

DAC output enabled, internal VREF, gain = 3 × or 4 × 325 400 485

Power supply rejection ratio

(dc)

Internal VREF, gain = 2 ×, DAC at midscale,

VDD = 5 V ±10% 0.25 mV/V

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6.5 Electrical Characteristics: Voltage Output (continued)

all minimum/maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,

DAC reference tied to VDD, gain = 1 ×, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive

load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DYNAMIC PERFORMANCE

tsett Output voltage settling time

1/4 to 3/4 scale and 3/4 to 1/4 scale settling to

10%FSR, VDD = 5.5 V 20

µs

1/4 to 3/4 scale and 3/4 to 1/4 scale settling to

10%FSR, VDD = 5.5 V, internal VREF, gain = 4 × 25

Slew rate VDD = 5.5 V 0.3 V/µs

Power-on glitch magnitude At start-up (DAC output disabled) 75 mV

At start-up (DAC output disabled), RL = 100 kΩ 200

Output-enable glitch

magnitude

DAC output disabled to enabled (DAC registers at zero

scale), RL = 100 kΩ 250 mV

VnOutput noise voltage (peak to

peak)

f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 50

µVPP

Internal VREF, gain = 4 ×, f = 0.1 Hz to 10 Hz,

DAC at midscale, VDD = 5.5 V 90

Output noise density

f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.35

µV/√Hz

Internal VREF, gain = 4 ×, f = 1 kHz, DAC at midscale,

VDD = 5.5 V 0.9

Power supply rejection ratio

(ac)(3)

Internal VREF, gain = 4 ×, 200-mV 50-Hz or 60-Hz sine

wave superimposed on power supply voltage, DAC at

midscale

-68 dB

Code change glitch impulse ±1 LSB change around midscale (including

feedthrough) 10 nV-s

Code change glitch impulse

magnitude

±1 LSB change around midscale (including

feedthrough) 15 mV

POWER

IDD Current flowing into VDD(4) (5) Normal operation, DACs at full scale, digital pins static,

external reference at VDD but the VREF pin is not

shorted to VDD

150 µA/ch

(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥ 1.21 × gain + 0.2 V, between end-point

codes: 32d to 4064d.

(2) Specified by design and characterization, not production tested.

(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.

(4) Measured with DAC output unloaded.

(5) The total power consumption is calculated by IDD × (total number of channels powered on) + (sleep-mode current).

(6) When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show

parametric drift.

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6.6 Electrical Characteristics: Current Output

all minimum/maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,

±250-µA output range, and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STATIC PERFORMANCE

Resolution 8 Bits

INL Integral nonlinearity DAC codes between 0d and 255d –1 1 LSB

DNL Differential nonlinearity DAC codes between 0d and 255d –1 1 LSB

Offset error DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and

±250 µA; DAC at midscale ±1 %FSR

Gain error DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and

±250 µA; DAC codes between 0d and 255d ±1.3 %FSR

OUTPUT

Output compliance voltage(1) DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and

±250 µA; to VDD and to AGND 400 mV

ZOIOUT dc output impedance(2) DAC at midscale, DAC output kept at VDD/2 60 MΩ

Power supply rejection ratio

(dc)

DAC at midscale, all bipolar ranges, VDD changed from

4.5V to 5.5V 0.23 LSB/V

DYNAMIC PERFORMANCE

tsett Output current settling time

1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 1 LSB

at 8-bit resolution, VDD = 5.5 V, common-mode voltage

at OUTx pin is VDD/2

60 µs

VnOutput noise current (peak to

peak)

0.1 Hz to 10 Hz, DAC at midscale,

VDD = 5.5 V, ±250-µA output range 150 nAPP

Output noise density f = 1 kHz, DAC at midscale,

VDD = 5.5 V, ±250-µA output range 1 nA/√Hz

Power supply rejection ratio

(ac)(3)

±250-µA output range, 200-mV 50-Hz or 60-Hz sine

wave superimposed on power-supply voltage, DAC at

midscale

0.65 LSB/V

POWER

IDD Current flowing into VDD(3) (4)

Normal operation, DACs at full scale, ±25-µA output

range, digital pins static 42 50

µA/ch

Normal operation, DACs at full scale, ±50-µA output

range, digital pins static 56 70

Normal operation, DACs at full scale, ±125-µA output

range, digital pins static 98 120

Normal operation, DACs at full scale, ±250-µA output

range, digital pins static 167 200

(1) Measured between DAC codes 0d and 255d.

(2) Specified by design and characterization, not production tested.

(3) The current flowing into VDD does not account for the load current sourced or sink on the OUTx pins. The VREF pin is connected to

VDD.

(4) The total power consumption is calculated by IDD × (total number of channels powered on) + (sleep-mode current).

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6.7 Electrical Characteristics: Comparator Mode

all minimum/maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,

DAC reference tied to VDD, gain = 1x in voltage output mode, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to

AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STATIC PERFORMANCE

Offset error(1) (2) 1.7 V ≤ VDD ≤ 5.5 V; DAC at midscale, comparator

input at Hi-Z, and DAC operating with external

reference.

–6 0 6 mV

Offset error time drift(1)

VDD = 5.5 V, external reference, TA = 125°C, FB in

Hi-Z mode, DAC at full scale and VFB at 0 V or DAC

at zero scale and VFB at 1.84 V, drift specified for 10

years of continuous operation

4 mV

OUTPUT

Input voltage

VREF connected to VDD, VFB resistor network

connected to ground 0 VDD

VREF connected to VDD, VFB resistor network

disconnected from ground 0

VDD

(1/3 –

1/100)

VOL Logic low output voltage ILOAD = 100 μA, output in open-drain mode 0.1 V

DYNAMIC PERFORMANCE

tresp Output response time

DAC at midscale with 10-bit resolution, FB input at

Hi-Z, and transition step at FB node is (VDAC –

2 LSB) to (VDAC + 2 LSB), transition time measured

between 10% and 90% of output, output current of

100 µA, comparator output configured in push-pull

mode, load capacitor at DAC output is 25 pF

10 µs

(1) Specified by design and characterization, not production tested.

(2) This specification does not include the total unadjusted error (TUE) of the DAC.

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6.8 Electrical Characteristics: General

all minimum/maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5

V, DAC reference tied to VDD, gain = 1 × in voltage output mode or ±250-µA output range in current output mode, DAC

output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) in voltage-output mode and capacitive load (CL = 200 pF to

AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL REFERENCE

Initial accuracy TA = 25°C 1.1979 1.212 1.224 V

Reference output temperature

coefficient(1) (2) 50 ppm/°C

EXTERNAL REFERENCE

VREF input impedance(1) (3) 192 kΩ/ch

EEPROM

Endurance(1) –40°C ≤ TA ≤ +85°C 20000 Cycles

TA = 125°C 1000

Data retention(1) TA = 25°C 50 Years

EEPROM programming write

cycle time(1) 200 ms

Device boot-up time(1) Time taken from power valid (VDD ≥ 1.7 V) to output

valid state (output state as programmed in EEPROM),

0.5-µF capacitor on the CAP pin

5 ms

DIGITAL INPUTS

Digital feedthrough Voltage output mode, DAC output static at midscale,

fast mode plus, SCL toggling 20 nV-s

IDD Current flowing into VDD DAC in sleep mode, internal reference powered down,

external reference at 5.5 V 28 µA

IDD Current flowing into VDD(1) DAC in sleep mode, internal reference

enabled, additional current through internal reference 10 µA

IDD Current flowing into VDD(1) DAC channels enabled, internal reference enabled,

additional current through internal reference per DAC

channel in voltage-output mode

12.5 µA

Pin capacitance Per pin 10 pF

POWER-DOWN MODE

HIGH-IMPEDANCE OUTPUT

ILEAK Current flowing into VOUTX and

VFBX

DAC in Hi-Z output mode, 1.7 V ≤ VDD ≤ 5.5 V 10 nA

VDD = 0 V, VOUT ≤ 1.5 V, decoupling capacitor between

VDD and AGND = 0.1 μF 200 nA

VDD = 0 V, 1.5 V < VOUT ≤ 5.5 V, decoupling capacitor

between VDD and AGND = 0.1 μF 500 nA

100 kΩ between VDD and AGND, VOUT ≤ 1.25 V, series

resistance of 10 kΩ at OUT pin ±2 µA

(1) Specified by design and characterization, not production tested.

(2) Measured at –40°C and +125°C and calculated the slope.

(3) Impedances for the DAC channels are connected in parallel.

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6.9 Timing Requirements: I2C Standard Mode

all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V

MIN NOM MAX UNIT

fSCLK SCL frequency 100 kHz

tBUF Bus free time between stop and start conditions 4.7 µs

tHDSTA Hold time after repeated start 4 µs

tSUSTA Repeated start setup time 4.7 µs

tSUSTO Stop condition setup time 4 µs

tHDDAT Data hold time 0 ns

tSUDAT Data setup time 250 ns

tLOW SCL clock low period 4700 ns

tHIGH SCL clock high period 4000 ns

tFClock and data fall time 300 ns

tRClock and data rise time 1000 ns

tVDDAT Data valid time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF 3.45 µs

tVDACK Data valid acknowledge time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF 3.45 µs

6.10 Timing Requirements: I2C Fast Mode

all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V

MIN NOM MAX UNIT

fSCLK SCL frequency 400 kHz

tBUF Bus free time between stop and start conditions 1.3 µs

tHDSTA Hold time after repeated start 0.6 µs

tSUSTA Repeated start setup time 0.6 µs

tSUSTO Stop condition setup time 0.6 µs

tHDDAT Data hold time 0 ns

tSUDAT Data setup time 100 ns

tLOW SCL clock low period 1300 ns

tHIGH SCL clock high period 600 ns

tFClock and data fall time 300 ns

tRClock and data rise time 300 ns

tVDDAT Data valid time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF 0.9 µs

tVDACK Data valid acknowledge time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF 0.9 µs

6.11 Timing Requirements: I2C Fast Mode Plus

all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V

MIN NOM MAX UNIT

fSCLK SCL frequency 1 MHz

tBUF Bus free time between stop and start conditions 0.5 µs

tHDSTA Hold time after repeated start 0.26 µs

tSUSTA Repeated start setup time 0.26 µs

tSUSTO Stop condition setup time 0.26 µs

tHDDAT Data hold time 0 ns

tSUDAT Data setup time 50 ns

tLOW SCL clock low period 0.5 µs

tHIGH SCL clock high period 0.26 µs

tFClock and data fall time 120 ns

tRClock and data rise time 120 ns

tVDDAT Data valid time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF 0.45 µs

tVDACK Data valid acknowledge time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF 0.45 µs

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