Texas Instruments MSP430G2955 Manuale utente

MSP430G2955

MSP430G2855

MSP430G2755

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SLAS800 –MARCH 2013

MIXED SIGNAL MICROCONTROLLER

Check for Samples: MSP430G2955,MSP430G2855,MSP430G2755

1FEATURES

• Low Supply-Voltage Range: 1.8 V to 3.6 V • Universal Serial Communication Interface

(USCI)

• Ultra-Low Power Consumption – Enhanced UART Supporting Auto Baudrate

– Active Mode: 250 µA at 1 MHz, 2.2 V Detection (LIN)

– Standby Mode: 0.7 µA – IrDA Encoder and Decoder

– Off Mode (RAM Retention): 0.1 µA – Synchronous SPI

• Five Power-Saving Modes – I2C™

• Ultra-Fast Wake-Up From Standby Mode in • On-Chip Comparator for Analog Signal

Less Than 1 µs Compare Function or Slope Analog-to-Digital

• 16-Bit RISC Architecture, 62.5-ns Instruction (A/D) Conversion

Cycle Time • 10-Bit 200-ksps Analog-to-Digital (A/D)

• Basic Clock Module Configurations Converter With Internal Reference, Sample-

– Internal Frequencies up to 16 MHz With and-Hold, and Autoscan

Four Calibrated Frequency • Brownout Detector

– Internal Very-Low-Power Low-Frequency • Serial Onboard Programming,

(LF) Oscillator No External Programming Voltage Needed,

– 32-kHz Crystal Programmable Code Protection by Security

– High-Frequency (HF) Crystal up to 16 MHz Fuse

– External Digital Clock Source • Bootstrap Loader

– External Resistor • On-Chip Emulation Logic

• Two 16-Bit Timer_A With Three • Family Members are Summarized in Table 1

Capture/Compare Registers • Package Options

• One 16-Bit Timer_B With Three – TSSOP: 38 Pin (DA)

Capture/Compare Registers – QFN: 40 Pin (RHA)

• Up to 32 Touch-Sense-Enabled I/O Pins • For Complete Module Descriptions, See the

MSP430x2xx Family User’s Guide (SLAU144)

DESCRIPTION

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430G2x55 series are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, up to 32

I/O touch-sense-enabled pins, a versatile analog comparator, and built-in communication capability using the

universal serial communication interface. For configuration details, see Table 1.

Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,

and then process the data for display or for transmission to a host system.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

1TEST/SBWTCK

2DVCC

3P2.5/TA1.0/ROSC

XOUT/P2.7 5

XIN/P2.6 6

RST/NMI/SBWTDIO 7

P2.0/TA1CLK/ACLK/A0 8

P2.1/TA0INCLK/SMCLK/A1 9

P2.2/TA0.0/A2 10

P3.0/UCB0STE/UCA0CLK/A5 11

P3.1/UCB0SIMO/UCB0SDA 12

P3.2/UCB0SOMI/UCB0SCL 13

P3.3/UCB0CLK/UCA0STE 14

P4.0/TB 00. /CA0

P4.1/TB 10. /CA1

P4.2/TB 20. /CA2

P4.3/TB 0/A120. /CA3

18 P4.4/TB 1/A130. /CA4

38 P1.7/TA 2/TDO/TDI0.

37 P1.6/TA 1/TDI0.

36 P1.5/TA 0/TMS0.

35 P1.4/SMCLK/TCK

34 P1.3/TA 20.

33 P1.2/TA 10.

32 P1.1/TA 00.

31 P1.0/TA0CLK/ADC10CLK

30 P2.4/TA 2/A4/VREF+/VEREF+0.

29 P2.3/TA 1/A3/VREF−/VEREF−0.

28 P3.7/TA1.2/A7

27 P3.6/TA1.1/A6

26 P3.5/UCA0RXD/UCA0SOMI

25 P3.4/UCA0TXD/UCA0SIMO

23AVCC

AVSS

P4.7/TB0CLK/CA7

P4.6/TB0OUTH/A15/CA6

DVSS

P4.5/TB 2/A140. /CA5

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Table 1. Available Options(1)(2)

Flash RAM Timer_A COMP_A+ ADC10 USCI_A0 Package

Device BSL EEM Clock I/O

(KB) (B) Timer_B Channels Channels USCI_B0 Type

MSP430G2955IDA38 HF, LF, 32 38-TSSOP

2x TA3

1 1 56 4096 8 12 1 DCO,

1x TB3

MSP430G2955IRHA40 32 40-QFN

VLO

MSP430G2855IDA38 HF, LF, 32 38-TSSOP

2x TA3

1 1 48 4096 8 12 1 DCO,

1x TB3

MSP430G2855IRHA40 32 40-QFN

VLO

MSP430G2755IDA38 HF, LF, 32 38-TSSOP

2x TA3

1 1 32 4096 8 12 1 DCO,

1x TB3

MSP430G2755IRHA40 32 40-QFN

VLO

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Device Pinout, 38-Pin TSSOP (DA Package)

Product Folder Links: MSP430G2955 MSP430G2855 MSP430G2755

Basic Clock

System+

RAM

Brownout

Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog

WDT+

15 or 16 Bit

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

56 kB

48 kB

32 kB

ACLK

XIN

MDB

MAB

Spy-Bi-Wire

3 CC

Registers,

Shadow

USCI_A0:

UART, LIN,

IrDA,SPI

USCI_B0:

SPI,I2C

ADC

10-Bit

Channels,

Autoscan,

DTC

Ports P1, P2

2x8 I/O,

Interrupt

capability,

Pullup or

pulldown

resistors

P1.x, P2.x

2x8

P3.x, P4.x

2x8

4 kB

Timer0_A3

3 CC

Registers

Timer1_A3

Timer0_B3

COMP_A+

Channels

Ports P3, P4

2x8 I/O,

Pullup or

pulldown

resistors

1DVSS

P1.5/TA0.0/TMS

P1.0/TA0CLK/ADC10CLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/SMCLK/TCK

P2.4/TA0.2/A4/VREF+/VEREF+

P2.5/TA1.0/ROSC

DVCC

TEST/SBWTCK

P1.6/TA0.1/TDI/TCLK

12 14 15 16 17 18 19

3839 37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/TA1CLK/ACLK/A0

P2.1/TA0INCLK/SMCLK/A1

P2.2/TA0.0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/TA0.2/TDO/TDI

P2.3/TA0.1/A3/VREF−/VEREF−

P3.7/TA1.2/A7

P3.6/TA1.1/A6

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

AVCC

AVSS

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB0.0/CA0

P4.1/TB0.1/CA1

P4.2/TB0.2/CA2

P4.3/TB0.0/A12/CA3

P4.4/TB0.1/A13/CA4

P4.5/TB0.2/A14/CA5

P4.6/TB0OUTH/A15/CA6

P4.7/TB0CLK/CA7

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Device Pinout, 40-Pin QFN (RHA Package)

Functional Block Diagram

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Table 2. Terminal Functions

TERMINAL

NO. I/O DESCRIPTION

NAME DA RHA

P1.0/ General-purpose digital I/O pin

TACLK/ 31 29 I/O Timer_A, clock signal TACLK input

ADC10CLK ADC10, conversion clock

P1.1/ General-purpose digital I/O pin

32 30 I/O

TA0.0 Timer_A, capture: CCI0A input, compare: OUT0 output or BSL transmit

P1.2/ General-purpose digital I/O pin

33 31 I/O

TA0.1 Timer_A, capture: CCI1A input, compare: OUT1 output

P1.3/ General-purpose digital I/O pin

34 32 I/O

TA0.2 Timer_A, capture: CCI2A input, compare: OUT2 output

P1.4/ General-purpose digital I/O pin

SMCLK/ 35 33 I/O SMCLK signal output

TCK JTAG test clock, input terminal for device programming and test

P1.5/ General-purpose digital I/O pin

TA0.0/ 36 34 I/O Timer_A, compare: OUT0 output

TMS JTAG test mode select, input terminal for device programming and test

P1.6/ General-purpose digital I/O pin /

TA0.1/ Timer_A, compare: OUT1 output

37 35 I/O

TDI/ JTAG test data input terminal during programming and test

TCLK JTAG test clock input terminal during programming and test

P1.7/ General-purpose digital I/O pin

TA0.2/ Timer_A, compare: OUT2 output

38 36 I/O

TDO/ JTAG test data output terminal during programming and test

TDI(1) JTAG test data input terminal during programming and test

P2.0/ General-purpose digital I/O pin

TA1CLK/ Timer1_A3.TACLK

8 6 I/O

ACLK/ ACLK output

A0 ADC10, analog input A0

P2.1/ General-purpose digital I/O pin

TAINCLK/ Timer_A, clock signal at INCLK

9 7 I/O

SMCLK/ SMCLK signal output

A1 ADC10, analog input A1

P2.2/ General-purpose digital I/O pin

TA0.0/ 10 8 I/O Timer_A, capture: CCI0B input or BSL receive, compare: OUT0 output

A2 ADC10, analog input A2

P2.3/ General-purpose digital I/O pin

TA0.1/ Timer_A, capture CCI1B input, compare: OUT1 output

A3/ 29 27 I/O ADC10, analog input A3

VREF-/ Negative reference voltage output

VEREF- Negative reference voltage input

P2.4/ General-purpose digital I/O pin

TA0.2/ Timer_A, compare: OUT2 output

A4/ 30 28 I/O ADC10, analog input A4

VREF+/ Positive reference voltage output

VEREF+ Positive reference voltage input

(1) TDO or TDI is selected via JTAG instruction.

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Table 2. Terminal Functions (continued)

TERMINAL

NO. I/O DESCRIPTION

NAME DA RHA

P2.5/ General-purpose digital I/O pin

TA1.0/ 3 40 I/O Timer_A, capture: CCI0B input or BSL receive, compare: OUT0 output

ROSC Input for external DCO resistor to define DCO frequency

XIN/ Input terminal of crystal oscillator

6 3 I/O

P2.6 General-purpose digital I/O pin

XOUT/ Output terminal of crystal oscillator

5 2 I/O

P2.7 General-purpose digital I/O pin(2)

P3.0/ General-purpose digital I/O pin

UCB0STE/ USCI_B0 slave transmit enable

11 9 I/O

UCA0CLK/ USCI_A0 clock input/output

A5 ADC10, analog input A5

P3.1/ General-purpose digital I/O pin

UCB0SIMO/ 12 10 I/O USCI_B0 slave in, master out in SPI mode

UCB0SDA USCI_B0 SDA I2C data in I2C mode

P3.2/ General-purpose digital I/O pin

UCB0SOMI/ 13 11 I/O USCI_B0 slave out, master in SPI mode

UCB0SCL USCI_B0 SCL I2C clock in I2C mode

P3.3/ General-purpose digital I/O pin

UCB0CLK/ 14 12 I/O USCI_B0 clock input/output

UCA0STE USCI_A0 slave transmit enable

P3.4/ General-purpose digital I/O pin

UCA0TXD/ 25 23 I/O USCI_A0 transmit data output in UART mode

UCA0SIMO USCI_A0 slave in, master out in SPI mode

P3.5/ General-purpose digital I/O pin

UCA0RXD/ 26 24 I/O USCI_A0 receive data input in UART mode

UCA0SOMI USCI_A0 slave out, master in SPI mode

P3.6/ General-purpose digital I/O pin

TA1.1/ 27 25 I/O Timer_A, capture: CCI1B input or BSL receive, compare: OUT2 output

A6 ADC10 analog input A6

P3.7/ General-purpose digital I/O pin

TA1.2/ 28 26 I/O Timer_A, capture: CCI2B input or BSL receive, compare: OUT2 output

A7 ADC10 analog input A7

P4.0/ General-purpose digital I/O pin

TB0.0/ 17 15 I/O Timer_B, capture: CCI0A input, compare: OUT0 output

CA0 Comparator_A+, CA0 input

P4.1/ General-purpose digital I/O pin

TB0.1/ 18 16 I/O Timer_B, capture: CCI1A input, compare: OUT1 output

CA1 Comparator_A+, CA1 input

P4.2/ General-purpose digital I/O pin

TB0.2/ 19 17 I/O Timer_B, capture: CCI2A input, compare: OUT2 output

CA2 Comparator_A+, CA2 input

(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

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Table 2. Terminal Functions (continued)

TERMINAL

NO. I/O DESCRIPTION

NAME DA RHA

P4.3/ General-purpose digital I/O pin

TB0.0/ Timer_B, capture: CCI0B input, compare: OUT0 output

20 18 I/O

A12/ ADC10 analog input A12

CA3 Comparator_A+, CA3 input

P4.4/ General-purpose digital I/O pin

TB0.1/ Timer_B, capture: CCI1B input, compare: OUT1 output

21 19 I/O

A13/ ADC10 analog input A13

CA4 Comparator_A+, CA4 input

P4.5/ General-purpose digital I/O pin

TB0.2/ Timer_B, compare: OUT2 output

22 20 I/O

A14/ ADC10 analog input A14

CA5 Comparator_A+, CA5 input

P4.6/ General-purpose digital I/O pin

TBOUTH/ Timer_B, switch all TB0 to TB3 outputs to high impedance

CAOUT/ 23 21 I/O Comparator_A+ Output

A15/ ADC10 analog input A15

CA6 Comparator_A+, CA6 input

P4.7/ General-purpose digital I/O pinCB0

TBCLK/ Timer_B, clock signal TBCLK input

24 22 I/O

CAOUT/ Comparator_A+ Output

CA7 Comparator_A+, CA7 input

RST/ Reset or nonmaskable interrupt input

7 5 I

NMI/SBWTDIO Spy-Bi-Wire test data input/output during programming and test

TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is

connected to TEST.

1 37 I

SBWTCK Spy-Bi-Wire test clock input during programming and test

DVCC 2 38, 39 Digital supply voltage

AVCC 16 14 Analog supply voltage

DVSS 4 1, 4 Digital ground reference

AVSS 15 13 Analog ground reference

QFN Pad NA Pad NA QFN package pad; connection to DVSS recommended.

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General-Purpose Register

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-Purpose Register

R10

R11

General-Purpose Register

R14

R15

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SHORT-FORM DESCRIPTION

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions, are

performed as register operations in conjunction with

seven addressing modes for source operand and four

addressing modes for destination operand.

The CPU is integrated with 16 registers that provide

reduced instruction execution time. The register-to-

CPU clock.

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register, and

constant generator, respectively. The remaining

registers are general-purpose registers.

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled with

all instructions.

The instruction set consists of the original 51

instructions with three formats and seven address

modes and additional instructions for the expanded

address range. Each instruction can operate on word

and byte data.

Instruction Set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 3 shows examples of the three types of

instruction formats; Table 4 shows the address

modes.

Table 3. Instruction Word Formats

INSTRUCTION FORMAT EXAMPLE OPERATION

Dual operands, source-destination ADD R4,R5 R4 + R5 ---> R5

Single operands, destination only CALL R8 PC -->(TOS), R8--> PC

Relative jump, un/conditional JNE Jump-on-equal bit = 0

Table 4. Address Mode Descriptions(1)

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) -- --> M(6+R6)

Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) -- --> M(TONI)

Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)

Indirect ✓MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)

M(R10) -- --> R11

Indirect autoincrement ✓MOV @Rn+,Rm MOV @R10+,R11 R10 + 2-- --> R10

Immediate ✓MOV #X,TONI MOV #45,TONI #45 -- --> M(TONI)

(1) S = source, D = destination

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Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the low-power modes, service the request, and restore back to the

low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM)

– All clocks are active.

• Low-power mode 0 (LPM0)

– CPU is disabled.

– ACLK and SMCLK remain active.

– MCLK is disabled.

• Low-power mode 1 (LPM1)

– CPU is disabled

– ACLK and SMCLK remain active.

– MCLK is disabled.

– DCO's dc generator is disabled if DCO not used in active mode.

• Low-power mode 2 (LPM2)

– CPU is disabled.

– ACLK remains active.

– MCLK and SMCLK are disabled.

– DCO's dc generator remains enabled.

• Low-power mode 3 (LPM3)

– CPU is disabled.

– ACLK remains active.

– MCLK and SMCLK are disabled.

– DCO's dc generator is disabled.

• Low-power mode 4 (LPM4)

– CPU is disabled.

– ACLK, MCLK, and SMCLK are disabled.

– DCO's dc generator is disabled.

– Crystal oscillator is stopped.

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the

CPU goes into LPM4 immediately after power-up.

Table 5. Interrupt Sources, Flags, and Vectors

SYSTEM WORD

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

INTERRUPT ADDRESS

Power-Up PORIFG

External Reset RSTIFG

Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest

Flash key violation KEYV(2)

PC out-of-range(1)

NMI NMIIFG (non)-maskable

Oscillator fault OFIFG (non)-maskable 0FFFCh 30

Flash memory access violation ACCVIFG(2)(3) (non)-maskable

Timer0_B3 TB0CCR0 CCIFG(4) maskable 0FFFAh 29

Timer0_B3 TB0CCR2 TB0CCR1 CCIFG, maskable 0FFF8h 28

TBIFG(2)(4)

Comparator_A+ CAIFG(4) maskable 0FFF6h 27

Watchdog Timer+ WDTIFG maskable 0FFF4h 26

Timer0_A3 TA0CCR0 CCIFG(4) maskable 0FFF2h 25

Timer0_A3 TA0CCR2 TA0CCR1 CCIFG, maskable 0FFF0h 24

TAIFG(5)(4)

USCI_A0 or USCI_B0 receive UCA0RXIFG, UCB0RXIFG(2)(5) maskable 0FFEEh 23

USCI_B0 I2C status

USCI_A0 or USCI_B0 transmit UCA0TXIFG, UCB0TXIFG(2)(6) maskable 0FFECh 22

USCI_B0 I2C receive or transmit

ADC10 ADC10IFG(4) maskable 0FFEAh 21

Reserved 0FFE8h 20

I/O Port P2 (up to eight flags) P2IFG.0 to P2IFG.7(2)(4) maskable 0FFE6h 19

I/O Port P1 (up to eight flags) P1IFG.0 to P1IFG.7(2)(4) maskable 0FFE4h 18

Timer1_A3 TA1CCR0 CCIFG(4) maskable 0FFE2h 17

Timer1_A3 TA1CCR2 TA1CCR1 CCIFG, maskable 0FFE0h 16

TAIFG(2)(4)

See (7) 0FFDEh 15

See (8) 0FFDEh to 14 to 0, lowest

0FFC0h

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address ranges.

(2) Multiple source flags

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4) Interrupt flags are located in the module.

(5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

(6) In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.

(7) This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)

disables the erasure of the flash if an invalid password is supplied.

(8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

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Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend rw: Bit can be read and written.

rw-0,1: Bit can be read and written. It is reset or set by PUC.

rw-(0,1): Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

Address 76543210

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog timer is configured in

interval timer mode.

OFIE Oscillator fault interrupt enable

NMIIE (Non)maskable interrupt enable

ACCVIE Flash access violation interrupt enable

Address 76543210

01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

rw-0 rw-0 rw-0 rw-0

UCA0RXIE USCI_A0 receive interrupt enable

UCA0TXIE USCI_A0 transmit interrupt enable

UCB0RXIE USCI_B0 receive interrupt enable

UCB0TXIE USCI_B0 transmit interrupt enable

Table 7. Interrupt Flag Register 1 and 2

Address 76543210

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.

OFIFG Flag set on oscillator fault.

PORIFG Power-on reset interrupt flag. Set on VCC power-up.

RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.

NMIIFG Set via RST/NMI pin

Address 76543210

03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

rw-1 rw-0 rw-1 rw-0

UCA0RXIFG USCI_A0 receive interrupt flag

UCA0TXIFG USCI_A0 transmit interrupt flag

UCB0RXIFG USCI_B0 receive interrupt flag

UCB0TXIFG USCI_B0 transmit interrupt flag

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Altri manuali Texas Instruments Microcontrollore

Texas Instruments

Texas Instruments TMS570LS0714 Manuale utente

Texas Instruments

Texas Instruments DRV8251/AEVM Manuale utente

Texas Instruments

Texas Instruments MSPM0G350 Series Manuale utente

Texas Instruments

Texas Instruments CC-6LOWPAN-DK-868 Manuale utente

Texas Instruments

Texas Instruments BP-DAC11001EVM Manuale utente

Texas Instruments

Texas Instruments MSP430F6733 Manuale utente

Texas Instruments

Texas Instruments AM243 Series Manuale utente

Texas Instruments

Texas Instruments MSP430x4xx Family Manuale utente

Texas Instruments

Texas Instruments MSP430FR6989 LaunchPad Manuale utente

Texas Instruments

Texas Instruments MSP430F42 series Manuale utente

Texas Instruments

Texas Instruments MSP430F6725A Manuale utente

Texas Instruments

Texas Instruments Delfino TMS320F28377D controlCARD Manuale tecnico

Texas Instruments

Texas Instruments LaunchPad C2000 F280015 Series Manuale utente

Texas Instruments

Texas Instruments CC1110 Manuale utente

Texas Instruments

Texas Instruments CC-Antenna-DK2 Manuale utente

Texas Instruments

Texas Instruments CC1110 Manuale di programmazione

Texas Instruments

Texas Instruments CC2543EMs Manuale utente

Texas Instruments

Texas Instruments LaunchPad MSP430G2553 Manuale utente

Texas Instruments

Texas Instruments MSP430F6721 Manuale utente

Texas Instruments

Texas Instruments LaunchPad LP-EM-CC2340R5 Manuale utente

Texas Instruments

Texas Instruments LaunchPad LP-CC1352P7-1 Manuale utente

Texas Instruments

Texas Instruments TUSB3210 Manuale utente

Texas Instruments

Texas Instruments MSP430F6768 Manuale utente

Texas Instruments

Texas Instruments CC3235MODASF Manuale utente

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AMS AS7261 Demo Kit Manuale utente

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Novatek NT6861 Manuale utente

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Espressif Systems ESP8266 SDK Guida all'installazione

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Nuvoton ISD61S00 ChipCorder Guida

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STMicrolectronics ST7 Assembler Linker Manuale utente

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Lantronix Intrinsyc Open-Q 865XR SOM Manuale utente

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NEC 78GK0S/K 1+ Series Istruzioni per l'installazione e il funzionamento

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Mikroe SEMITECH N-PLC Click Istruzioni per l'installazione e il funzionamento

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Intel Agilex Manuale utente

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Cypress CY4607 HX2VL Manuale utente

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DIGITAL-LOGIC MICROSPACE Manuale utente

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CYPRES CY14NVSRAMKIT-001 Manuale utente

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Espressif Systems ESP8266EX Istruzioni operative

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Abov AC33M8128L Manuale utente

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Laird BL654PA Manuale utente

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Silicon Laboratories C8051F800 Manuale utente

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Energy micro EFM32 Giant Gecko Starter Kit Manuale utente

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