Texas Instruments ISO154 EVM Series Manuale utente

User's Guide

SLLU166–June 2012

ISO154xEVM Low-Power Bidirectional I2C Isolators

Evaluation Module

Contents

1 Introduction .................................................................................................................. 2

1.1 Overview ............................................................................................................ 2

1.2 ISO154xEVM Kit Contents ........................................................................................ 2

1.3 Functional Configuration .......................................................................................... 3

1.4 EVM Schematic .................................................................................................... 4

2 EVM Setup and Operation ................................................................................................. 6

2.1 Overview ............................................................................................................ 6

2.2 Input/Output Signal Characteristics .............................................................................. 7

3 Bill of Materials .............................................................................................................. 9

4 ISO154xEVM Layout ...................................................................................................... 10

List of Figures

1 ISO1540 and ISO1541 Pinout............................................................................................. 3

2 ISO154xEVM Top Photograph............................................................................................ 3

3 ISO154xEVM Schematic................................................................................................... 4

4 Basic EVM Operation....................................................................................................... 6

5 Typical Waveforms, Inputs on Side 1 .................................................................................... 7

6 Typical Waveforms, Inputs on Side 2 .................................................................................... 8

7 ISO154xEVM Top-layer Routing ........................................................................................ 10

8 ISO154xEVM Bottom-layer Ground Planes............................................................................ 11

List of Tables

1 ISO154xEVM Description.................................................................................................. 5

2 ISO154x EVM Bill of Materials ............................................................................................ 9

SLLU166–June 2012 ISO154xEVM Low-Power Bidirectional I2C Isolators Evaluation Module

Introduction

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1 Introduction

This User’s Guide details the ISO154x Evaluation Module (EVM) operation of the factory-installed

ISO1540 and ISO1541 I2C-compatible bidirectional isolators. The EVM may be reconfigured for use with

two ISO1540 or two ISO1541 instead of one of each.

This Guide presents a typical laboratory setup used with this EVM.

CAUTION

This Evaluation Module (EVM) is made available for isolator parameter

performance evaluation only and is not intended for isolation voltage testing. To

prevent damage to the EVM, any voltage applied as a supply or digital

input/output must be maintained within the 0 V to 5.5 V recommended

operating range.

Exceeding the specified input voltage range may cause unexpected operation and irreversible damage to

the EVM. If there are questions concerning the input voltage range, contact a TI field representative prior

to connecting power.

Applying loads outside the specified output range may result in unintended operation and possible

permanent damage to the EVM. If there is uncertainty as to the load specification, contact a TI field

representative.

1.1 Overview

The ISO154x devices are low-power, bidirectional isolators that are compatible with I2C interfaces. The

logic input and output buffers on these devices are separated by TI’s Capacitive Isolation technology

utilizing a silicon dioxide (SiO2) barrier. When used in conjunction with isolated power supplies, these

devices block high voltages, isolate grounds and prevent noise currents from entering the local ground

and interfering with or damaging sensitive circuitry.

The ISO1540 has two isolated bidirectional channels for clock and data lines and is fit for multi-master

applications. The ISO1541 has a bidirectional data and a unidirectional clock channel and is useful in

applications that have a single master.

These devices achieve isolated bidirectional communication by introducing an offset, making the side 1

low-level output greater than the side 1 low-level input and thus preventing an internal logic latch that

otherwise would occur with standard digital isolators.

1.2 ISO154xEVM Kit Contents

1. ISO154xEVM Circuit Board (PWB P/N 6547206)

2. ISO154xEVM User’s Guide (SLLU166 - this document)

3. ISO154x Datasheet (SLLSEB6)

2SLLU166–June 2012

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ISO1540

GND2

SCL1

VCC2

VCC1

SCL2

Side 1

SDA1 SDA2

Isolation

ISO1541

GND2

SCL1

VCC2

VCC1

SCL2

GND1

SDA1 SDA2

Isolation

Side 2 Side 1 Side 2

GND1

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Introduction

1.3 Functional Configuration

The pinouts of ISO1540 and ISO1541 are displayed in Figure 1. These devices have an input noise-filter

that prevents transient pulses of up to 5 ns from being passed to the output of the device.

Figure 1. ISO1540 and ISO1541 Pinout

The EVM is shown in Figure 2, it comes with an ISO1540 and an ISO1541 installed in place of U1 and U2

respectively. However, this EVM can be configured for use with two ISO1540s or two ISO1541s.

Figure 2. ISO154xEVM Top Photograph

An input or output pin can be tied either to supply voltage (VCCx) or Ground (GNDx) using the 4-pin

jumpers on the EVM (J3A to J10A on side 1 and J3B to J10B on side 2). These jumpers also provide

scope-probe access to each pin.

Each signal line (SDAx, SCLx) is configured with a 1-kΩpull-up resistor (R1 to R8) to the corresponding

power supply (VCCx). Reconfigure the value of this pull-up resistor as per the application requirement.

SLLU166–June 2012 ISO154xEVM Low-Power Bidirectional I2C Isolators Evaluation Module

Introduction

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1.4 EVM Schematic

A schematic diagram for this EVM is presented in Figure 3.

Figure 3. ISO154xEVM Schematic

4SLLU166–June 2012

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Introduction

Table 1. ISO154xEVM Description

Label Description

U1 ISO154x, by default populated as ISO1540

U2 ISO154x, by default populated as ISO1541

J1 Side 1 power supply terminal block (VCC1)

J2 Side 2 power supply terminal block (VCC2)

TP15, TP47 Side 1 GND test point (GND1)

TP18, TP34 Side 2 GND test point (GND2)

TP13 VCC1 test point

TP16 VCC2 test point

J3A, J4A 4-pin jumper to VCC1, SDA1, GND1 for U1

J5A, J6A 4-pin jumper to VCC1, SCL1, GND1 for U1

J3B, J4B 4-pin jumper to VCC2, SDA2, GND2 for U1

J5B, J6B 4-pin jumper to VCC2, SCL2, GND2 for U1

J7A, J8A 4-pin jumper to VCC1, SDA1, GND1 for U2

J9A, J10A 4-pin jumper to VCC1, SCL1, GND1 for U2

J7B, J8B 4-pin jumper to VCC2, SDA2, GND2 for U2

J9B, J10B 4-pin jumper to VCC2, SCL2, GND2 for U2

C1, C2, C3, C4 1.0 µF filter capacitor

C5, C6, C7, C8 0.1 µF filter capacitor

R1, R2, R5, R6 1-kΩ0603 footprint pull-up resistor to VCC1

R3, R4, R7, R8 1-kΩ0603 footprint pull-up resistor to VCC2

SLLU166–June 2012 ISO154xEVM Low-Power Bidirectional I2C Isolators Evaluation Module

J1 J2

J3A/J4A

J5A/J6A

J3B/J4B

J5B/J6B

J7A/J8A

J9A/J10A

J7B/J8B

J9B/J10B

Power Supply

VCC1

Power Supply

VCC2

I C Transmitter

Oscilloscope I C Transmitter

Oscilloscope

EVM Setup and Operation

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2 EVM Setup and Operation

This section includes the setup and operation of the EVM for parameter performance evaluation. Typical

input and output waveforms are included.

2.1 Overview

The basic setup in Figure 4 has the two power supplies required to evaluate isolator performance with any

combination of 3.3 V or 5 V on either side. If both sides are evaluated at the same supply voltage, only

one power supply is required and can be used to power both sides of the EVM.

CAUTION

Note that this EVM is for operating parameter performance evaluation only and

not designed for isolation voltage testing. Any voltage applied above the 5.5-V

maximum recommended operating voltage of the isolators may damage the

EVM.

Please note that if the ISO1541 is used, providing an input signal on the SCL2 pin does not yield any

output on SCL1, SCL1 remains pulled up to VCC1.

Figure 4. Basic EVM Operation

6SLLU166–June 2012

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EVM Setup and Operation

2.2 Input/Output Signal Characteristics

Figure 5 illustrates SDA1 and SCL1 of U1 being treated as inputs and driven by an I2C transmitter

connected to J3A/J4A (for SDA1) and J5A/J6A (for SCL1). The output waveforms at SDA2 and SCL2 are

captured on the oscilloscope at J3B/J4B and J5B/J6B respectively. Note the step in the rising edge of the

input waveforms at SDA1 and SCL1 indicative of the tLOOP parameter of the device and demonstrating

the effect of the difference in the low levels for the side 1 output and input enabling the device to avoid a

latch-up state.

Note the tLOOP effect on the rising edge of the input waveforms on SDA1 and SCL1.

Figure 5. Typical Waveforms, Inputs on Side 1

SLLU166–June 2012 ISO154xEVM Low-Power Bidirectional I2C Isolators Evaluation Module

EVM Setup and Operation

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Figure 6 illustrates SDA2 and SCL2 of U1 being treated as inputs and driven by an I2C transmitter

connected to J3B/J4B (for SDA2) and J5B/J6B (for SCL2). The output waveforms for SDA1 and SCL1 are

captured on the oscilloscope at J3A/J4A and J5A/J6A respectively. Note the low level of the SDA1 and

SCL1 outputs offset from the ground level. This is due to the high output low level on side 1 designed to

prevent a latch-up state.

Note the offset of the output low level voltage from ground on SDA1 and SCL1.

Figure 6. Typical Waveforms, Inputs on Side 2

In addition to the cases shown here, the SDA and SCL signals also propagate in mutually opposing

directions. However, if using ISO1541, the SCL line is unidirectional and only allows the signal to

propagate from SCL1 to SCL2 and not vice-versa.

8SLLU166–June 2012

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Bill of Materials

3 Bill of Materials

The parts list for the ISO154xEVM is shown in Table 2.

Table 2. ISO154x EVM Bill of Materials

Item Qty. References Part Manufacturer

CAPACITOR, SMT, 0603, CERAMIC, 1.0 µF, 25 V, 10%,

1 4 C1,C2,C3,C4 TAIYO_YUDEN/ANY

X5R

CAPACITOR, SMT, 0603, CERAMIC, 1.0 µF, 25 V, 10%,

2 4 C5,C6,C7,C8 TAIYO_YUDEN/ANY

X5R

3 2 J1,J2 CONNECTOR, THU, TERMINAL BLOCK, 2.54 mm LS, 2P TYCO/ANY

4 8 R1,R2,R3,R4,R5,R6,R7,R8 RESISTOR, SMT, 0603, 1.0 kΩ, 0.1%, 1/10W PANASONIC/ANY

TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP9,

TP10,TP11,TP12,TP13,TP14,TP15,TP16,

TP17,TP18,TP19,TP20,TP21,TP22,TP23,

TP24,TP25,TP26,TP27,TP28,TP29,TP30,

TP31,TP32,TP33,TP34,TP35,TP36,TP37,

5 70 HEADER, THU, 1P, MALE, SINGLE ROW SAMTEC/ANY

TP38,TP39,TP40,TP41,TP42,TP43, TP44,

TP45,TP46,TP47,TP48,TP49,TP50,TP51,

TP52,TP53,TP54,TP55,TP56,TP57,TP58,

TP59,TP60,TP61,TP62,TP63,TP64,TP65,

TP66,TP67,TP68,TP69,TP70

6 1 U1 IC, ISO1540, SMT, SOIC8D TI

7 1 U2 IC, ISO1541, SMT, SOIC8D TI

8 4 Rubber feet, SJ5303, Bumpon hemisphere 2M

Notes: 1. J3A on EVM silkscreen is TP30, TP63, TP33, TP32 grouped as single row 4-pin jumper.

2. J4A on EVM silkscreen is TP23, TP5, TP17, TP25 grouped as single row 4-pin jumper.

3. J5A on EVM silkscreen is TP36, TP65, TP39, TP38 grouped as single row 4-pin jumper

4. J6A on EVM silkscreen is TP27, TP6, TP20, TP24 grouped as single row 4-pin jumper.

5. J3B on EVM silkscreen is TP35, TP66, TP34, TP37 grouped as single row 4-pin jumper.

6. J4B on EVM silkscreen is TP29, TP7, TP2, TP26 grouped as single row 4-pin jumper.

7. J5B on EVM silkscreen is TP41, TP64, TP40, TP43 grouped as single row 4-pin jumper.

8. J6B on EVM silkscreen is TP31, TP8, TP4, TP28 grouped as single row 4-pin jumper

9. J7A on EVM silkscreen is TP44, TP68, TP47, TP46 grouped as single row 4-pin jumper.

10. J8A on EVM silkscreen is TP42, TP9, TP19, TP45 grouped as single row 4-pin jumper.

11. J9A on EVM silkscreen is TP49, TP69, TP51, TP50 grouped as single row 4-pin jumper.

12. J10A on EVM silkscreen is TP48, TP10, TP22, TP53 grouped as single row 4-pin jumper.

13. J7B on EVM silkscreen is TP54, TP70, TP57, TP56 grouped as single row 4-pin jumper.

14. J8B on EVM silkscreen is TP52, TP11, TP3, TP55 grouped as single row 4-pin jumper.

15. J9B on EVM silkscreen is TP61, TP67, TP60, TP62 grouped as single row 4-pin jumper.

16. J10B on EVM silkscreen is TP58, TP12, TP1, TP59 grouped as single row 4-pin jumper.

17. SJ5303 Bumpon Hemisphere: one each to be assembled at every corner of the board on the bottom side.

SLLU166–June 2012 ISO154xEVM Low-Power Bidirectional I2C Isolators Evaluation Module

ISO154xEVM Layout

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4 ISO154xEVM Layout

Figure 7 shows the top-layer routing of the ISO154xEVM.

Figure 7. ISO154xEVM Top-layer Routing

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