Texas Instruments PCM1840EVM Manuale utente

SBAU345–March 2020

PCM1840 Evaluation Module

User's Guide

SBAU345–March 2020

PCM1840 Evaluation Module

This user's guide describes the function and use of the PCM1840EVM. This document includes the

hardware configuration instructions, a quick-start guide, jumper and connector descriptions, schematics,

and printed-circuit board (PCB) layout that demonstrate TI's recommended practices for these devices.

Contents

1 Introduction ................................................................................................................... 3

2 Power Supply................................................................................................................. 3

3 Hardware Configuration..................................................................................................... 3

3.1 PCM1840EVM Inputs .............................................................................................. 5

4 EVM Overview ............................................................................................................... 6

5 Layer Plots.................................................................................................................... 8

6 Schematic and Bill of Materials........................................................................................... 11

6.1 PCM1840EVM Schematic........................................................................................ 11

6.2 PCM1840EVM Bill of Materials.................................................................................. 13

7 Related Documentation.................................................................................................... 15

List of Figures

1 PCM1840EVM Input Architecture ......................................................................................... 5

2 PCM1840EVM Connection for Line Input Application .................................................................. 5

3 PCM1840EVM Connection for the Onboard Microphone Test ........................................................ 6

4 EVM Front Overview ........................................................................................................ 6

5 EVM Back Overview ........................................................................................................ 7

6 Top Layer..................................................................................................................... 8

7 Power Plane 1................................................................................................................ 9

8 Power Plane 2.............................................................................................................. 10

9 Bottom Layer................................................................................................................ 11

10 PCM1840EVM Schematics - Main....................................................................................... 12

11 PCM1840 Schematics - Power........................................................................................... 12

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List of Tables

1 PCM1840 EVM Headers and Jumpers................................................................................... 3

2 PCM1840 Hardware Controllable Settings............................................................................... 4

3 PCM1840EVM Bill of Materials........................................................................................... 13

Trademarks

Burr-Brown is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

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Introduction

SBAU345–March 2020

PCM1840 Evaluation Module

1 Introduction

The PCM1840EVM is an evaluation module (EVM) designed to demonstrate the performance and

functionality of the PCM1840 device. The PCM1840 is a high-performance audio analog-to-digital

converter (ADC) that is configured through logic-level mode selection pins and does not require a digital

interface such as I2C or SPI to configure registers. As such, no software is necessary to interface with the

EVM. The EVM is powered with a single 5-V supply. Access to the converter output is provided on the

audio serial interface in I2S, LJ, or TDM format.

2 Power Supply

The PCM1840EVM can be powered with a single 5-V power supply connected to J6. Onboard low dropout

regulators convert the 5-V supply to the 3.3-V and 1.8-V rails used by the ADC. The analog supply,

AVDD, is fixed at 3.3 V. The digital supply, IOVDD, can be set to either 1.8 V or 3.3 V with J5. It is also

possible to power the ADC directly by removing J9 and J5 and applying a voltage directly to the AVDD

and IOVDD test points. Note that if this is done, it is important to keep J10 populated (or ensure there is a

path between the pins if the supply current is being monitored) as this jumper connects the applied IOVDD

to the mode selection pins and other circuitry that relies on IOVDD. If external supplies are used, there is

an onboard voltage supervisor, U3, that will hold the ADC in shutdown until both AVDD and IOVDD have

reached their respective threshold voltages. The shutdown thresholds for the supply voltages can be

adjusted as shown in Equation 1 and Equation 2. The supervisor can also be removed from the shutdown

logic by depopulating R5. For more information on the reset supervisor, see the TPS37xx Dual-Channel,

Low-Power, High-Accuracy Voltage Detectors Data Sheet.

(1)

(2)

3 Hardware Configuration

The format of the audio data and the operating mode of the ADC are controlled by the following pins:

MD0, MD1, MSZ, FMT0, and FMT1. These signals are referenced to IOVDD and can be set to high (1) or

low (0). If no shunt is installed, then a 10-kΩpulldown resistor will set the pin low so that the ADC remains

in a defined state. Table 1 shows the header numbers and their pin functions and Table 2 shows the

possible modes and output formats. The MSZ pin selects whether the device is a master or a slave on the

audio bus. When MSZ is pulled high, the device is in slave mode and MD1 becomes an input for MCLK. A

shunt connecting J19 to the center pin of J18 will route the MCLK signal provided on J8 to the MD1 pin on

the ADC to allow for easy interfacing with audio measurement equipment.

Table 1. PCM1840 EVM Headers and Jumpers

Designator Function

J1 Differential line, microphone input 1

J2 Differential line, microphone input 2

J3 Differential line, microphone input 3

J4 Differential line, microphone input 4

J5 IOVDD-SYS voltage selection (1.8 V or 3.3 V)

J6 +5-V supply input

J7 Connector to AC-MB

J8 Digital audio serial interface

J9 Connect AVDD to onboard 3.3-V regulator

J10 Connect IOVDD to IOVDD-SYS

J13 MSZ select

J14 Connect MICBIAS to onboard microphone

J15 Microphone OUT+ to ADC IN1P

Hardware Configuration

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Table 1. PCM1840 EVM Headers and Jumpers (continued)

Designator Function

J16 Microphone OUT– to ADC IN1M

J17 MDO select

J18 MD1 select

J19 Connect MCLK to MD1

J20 FMT0 select

J21 FMT1 select

Table 2. PCM1840 Hardware Controllable Settings

MD0 Modes

MD0 MSZ (0 = Slave, 1 = Master) MDO Functional Mode

0 0 Linear phase filter

0 1 MCLK = 256 × Fs

1 0 Low latency filter

1 1 MCLK = 512 × Fs

MD1 Modes

MD1 MSZ (0 = Slave, 1 = Master) MD1 Functional Mode

0 0 DRE disabled

0 1 MCLK input

1 0 DRE enabled

1 1 MCLK input

Audio Output Data Format

FMT0 FMT1 Data Format

0 0 4 channel TDM

0 1 2 channel TDM

1 0 2 channel left-justified

1 1 2 channel I2S

All hardware pins are tied low by default, placing the device in slave mode with a linear phase filter, DRE

disabled, and 4-channel TDM audio output.

For more information on the operating modes of the PCM1840 device, see the PCM1840 Quad Channel,

32-Bit, 192-kHz, Burr-Brown™ Audio ADC Data Sheet.

MK1

IN1P IN1M IN2P IN2M IN3P IN3M IN4P IN4M

PCM1840

IN1P IN1M IN2P IN2M IN3P IN3M IN4P IN4M

J16

J15

MICBIAS

J14

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Hardware Configuration

SBAU345–March 2020

PCM1840 Evaluation Module

3.1 PCM1840EVM Inputs

The PCM1840 device is intended to be driven with differential line inputs or microphone inputs. Each of

the inputs has a 1-µF AC coupling film capacitor. Coupled with the 2.5-kΩinput impedance, this sets the

high pass filter cutoff frequency at approximately 63 Hz. This can be adjusted by replacing the input AC

coupling capacitors on the EVM if necessary. Figure 1 shows the architecture of the inputs to the

evaluation module. The EVM supports a differential full scale input range of 2 VRMS with an AVDD of 3.3 V.

Figure 1. PCM1840EVM Input Architecture

3.1.1 Line Inputs

For the line input configuration, shown in Figure 2, the PCM1840 captures the audio signal provided

through terminals J1 (IN1), J2 (IN2), J3 (IN3), and J4 (IN4). The input accepted in this mode is a

differential, 2 VRMS, full-scale audio signal. Single-ended inputs are not supported by the PCM1840 device

and the inputs should be AC coupled.

Figure 2. PCM1840EVM Connection for Line Input Application

EVM Overview

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3.1.2 Onboard Microphone Input

For the onboard microphone input configuration (shown in Figure 3), the PCM1840EVM records the audio

captured from the microphone located on the bottom-left edge of the board. MICBIAS is used to power the

onboard microphone through J14. J15, and J16 must be installed to connect the microphone output to the

ADC inputs. There must not be any connections to J1 during onboard microphone use to preserve the

performance of the microphone.

Figure 3. PCM1840EVM Connection for the Onboard Microphone Test

4 EVM Overview

Figure 4 shows an overview of the system.

Figure 4. EVM Front Overview

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EVM Overview

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PCM1840 Evaluation Module

Figure 5. EVM Back Overview

Layer Plots

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5 Layer Plots

Figure 6. Top Layer

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Layer Plots

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Figure 7. Power Plane 1

Layer Plots

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PCM1840 Evaluation Module

Figure 8. Power Plane 2

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