WinSystems PCM-UIO48B Manuale utente
OPERATIONS MANUAL
PCM-UIO48B
NOTE: This manual has been designed and created for use as part of the WinSystems Technical Manuals
CD and/or the WinSystems website. If this manual or any portion of the manual is downloaded, copied or
emailed, the links to additional information (i.e. software, cable drawings) may be inoperable.
WinSystems reserves the right to make changes in the circuitry
and specications at any time without notice.
Copyright 2011 by WinSystems. All Rights Reserved.
REVISION HISTORY
P/N 403-0321-000
ECO Number Date Code Rev Level
ORIGINATED 110425 A
Table of Contents
Visual Index – Quick Reference i
Top View - Connectors i
Introduction 1
General Information 1
Features 1
General Description 1
Functional Capability 2
I/O Address Selection 2
Interrupt Routing 2
Digital I/O 3
PC/104 Bus Interface 4
Software Summary 5
WS16C48 Programming Reference 7
Sample Programs 11
Summary 11
C Source Code Listings 12
Cables 28
Software Drivers & Examples 28
Jumper Reference 29
Specications 32
WARRANTY REPAIR INFORMATION 33
110425 OPERATIONS MANUAL PCM-UIO48B i
Visual Index – Quick Reference
Top View - Connectors
For the convenience of the user, a copy of the Visual Index has been provided with
direct links to connector and jumper conguration data.
J1
Ports 3-5 I/O
Connector
J2
Ports 0-2 I/O
Connector
J6
Auxillary
Interrupt
Routing Header
J5
PC/104 Bus
(8-bit, 16-bit)
Connector
J3
Base I/O
Address
Selection
Jumper
J4
Interrupt
Routing
Header
NOTE: The reference line to each component part has been drawn to Pin 1, where applicable.
Pin 1 is also highlighted with a red square, where applicable.
110425 OPERATIONS MANUAL PCM-UIO48B 1
This manual is intended to provide the necessary information regarding conguration and
usage of the PCM-UIO48B board. WinSystems maintains a Technical Support Group to help
answer questions regarding usage or programming of the board. For answers to questions not
adequately addressed in this manual, contact Technical Support at (817) 274-7553, Monday
through Friday, between 8 AM and 5 PM Central Standard Time (CST).
General Information
Introduction
Features
General Description
The PCM-UIO48B is a highly versatile PC/104 input/output module providing 48 lines of
digital I/O. It is unique in its ability to monitor 24 lines for both rising and falling digital edge
transitions, latch them, and then issue an interrupt to the host processor. The application
interrupt service routine can quickly determine, through a series of interrupt identication
registers, the exact port(s) and bit(s) which have transitioned. The PCM-UIO48B utilizes
WinSystems’ WS16C48 ASIC High Density I/O (HDIO) Chip. The rst 24 lines are capable of
fully latched event sensing with the sense polarity being software programmable. Two 50-pin
I/O connectors allow for easy mating with industry standard I/O racks.
Digital I/O
• 48 Bidirectional lines with Input, Output or Output with Readback (WS16C48)
• 12 mA Sink Current
Event Sense
• Supports 24 event sense lines
• Programmable polarity for each line
• Software-enabled interrupt for each Line
• Change-of-state latched for each line
Power
• +5V @ 12 mA required
Industrial Operating Temperature Range
• -40°C to 85°C
Form Factor
• PC/104-compliant
• 3.60” x 3.80” (90 mm x 96 mm)
Additional Specications
• Compatible with industry standard I/O racks
• Write-protection mask register for each port
• Fused +5V logic supply for I/O modules
• 8-bit, 16-bit PC/104 Interface
110425 OPERATIONS MANUAL PCM-UIO48B 2
The PCM-UIO48B requires 16 consecutive I/O addresses beginning on an 16-byte
boundary. The jumper block at J3 allows for user selection of the base address.
Address selection is made by placing a jumper on the jumper pair for the address
bit, if a 0 is desired or leaving the jumper pair open if a 1 is required for the desired
address. The illustration below shows the relationship between the address bit and the
jumper position and a sample jumpering for an address of 200H.
Functional Capability
I/O Address Selection
Interrupt Routing
The PCM-UIO48B can generate an interrupt on up to 24 different lines each with its
own polarity select. Interrupt support is provided on the rst 24 bits of each device for
ports 0, 1 and 2. This interrupt can be routed to the PC/104 bus via the jumper at J4.
16-bit versions of the board will also have the auxillary jumper at J6 installed. The
interrupt routing header is shown below along with sample jumpering for IRQ5.
A11
A10
A9
A8
A7
A6
A5
A4
J3
I/O Base Address Select jumper
J3 shown jumpered for 200H
1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16
J6
1 o
2 o
3 o
4 o
5 o
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
J4
110425 OPERATIONS MANUAL PCM-UIO48B 3
Digital I/O
1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16
17 o o 18
19 o o 20
21 o o 22
23 o o 24
25 o o 26
27 o o 28
29 o o 30
31 o o 32
33 o o 34
35 o o 36
37 o o 38
39 o o 40
41 o o 42
43 o o 44
45 o o 46
47 o o 48
49 o o 50
P2-7
P2-6
P2-5
P2-4
P2-3
P2-2
P2-1
P2-0
P1-7
P1-6
P1-5
P1-4
P1-3
P1-2
P1-1
P1-0
P0-7
P0-6
P0-5
P0-4
P0-3
P0-2
P0-1
P0-0
+5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J2
1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16
17 o o 18
19 o o 20
21 o o 22
23 o o 24
25 o o 26
27 o o 28
29 o o 30
31 o o 32
33 o o 34
35 o o 36
37 o o 38
39 o o 40
41 o o 42
43 o o 44
45 o o 46
47 o o 48
49 o o 50
P5-7
P5-6
P5-5
P5-4
P5-3
P5-2
P5-1
P5-0
P4-7
P4-6
P4-5
P4-4
P4-3
P4-2
P4-1
P4-0
P3-7
P3-6
P3-5
P3-4
P3-3
P3-2
P3-1
P3-0
+5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J1
NOTE:
Pin 49 on each connector can supply +5V to the I/O rack. The supply on each connector
is protected from excessive current by a 1A miniature fuse F1 for J1 and F2 for J2.
The PCM-UIO48B routes its 48 lines to 50-pin IDC connectors at J1 and J2. The pin
denitions for J1 and J2 are shown below.
110425 OPERATIONS MANUAL PCM-UIO48B 4
PC/104 Bus Interface
The PCM-UIO48B connects to the processor through the PC/104 bus connector at
J5. The pin denitions for the 8-bit and 16-bit extension of J5 are provided here for
reference. Refer to the PC/104 Bus Specication for specic signal and mechanical
specications.
D0 o o C0
D1 o o C1
D2 o o C2
D3 o o C3
D4 o o C4
D5 o o C5
D6 o o C6
D7 o o C7
D8 o o C8
D9 o o C9
D10 o o C10
D11 o o C11
D12 o o C12
D13 o o C13
D14 o o C14
D15 o o C15
D16 o o C16
D17 o o C17
D18 o o C18
D19 o o C19
GND
MEMCS16#
IOCS16#
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DACK0#
DRQ0
DACK5#
DRQ5
DACK6#
DRQ6
DACK7#
DRQ7
+5V
MASTER#
GND
GND
GND
SBHE#
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR#
MEMW#
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
KEY
A1 o o B1
A2 o o B2
A3 o o B2
A4 o o B4
A5 o o B5
A6 o o B6
A7 o o B7
A8 o o B8
A9 o o B9
A10 o o B10
A11 o o B11
A12 o o B12
A13 o o B13
A14 o o B14
A15 o o B15
A16 o o B16
A17 o o B17
A18 o o B18
A19 o o B19
A20 o o B20
A21 o o B21
A22 o o B22
A23 o o B23
A24 o o B24
A25 o o B25
A26 o o B26
A27 o o B27
A28 o o B28
A29 o o B29
A30 o o B30
A31 o o B31
A32 o o B32
GND
RESET
+5V
IRQ9
-5V
DRQ2
-12V
SRDY#
+12V
KEY
SMEMW#
SMEMR#
IOW#
IOR#
DACK3#
DRQ3
DACK1#
DRQ1
REFRESH#
BCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2#
TC
BALE
+5V
OSC
GND
GND
IOCHK#
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
GND
NOTES:
1. Rows C and D are not required on 8-bit modules.
2. B10 and C19 are key locations. WinSystems uses key pins as connections to GND.
3. Signal timing and function are as specied in ISA specication.
4. Signal source/sink current differ from ISA values.
# = Active Low Signal
110425 OPERATIONS MANUAL PCM-UIO48B 5
WS16C48 Register Denitions – The PCM-UIO48B uses the WinSystems exclusive ASIC device,
the WS16C48. This device provides 48 lines of digital I/O. There are 17 unique registers within
the WS16C48. The following table summarized the registers and the text that follows provides
details on each of the internal registers.
Register Details
Port 0 through 5 I/O – Each I/O bit in each of the six ports can be individually programmed
for input or output. Writing a 0to a bit position causes the corresponding output pin to go to a
high-impedance state (pulled high by external 10 KΩ resistors). This allows it to be used as an
input. When used in the input mode, a read reects the inverted state of the I/O pin, such that
a high on the pin will read as a 0 in the register. Writing a 1to a bit position causes that output
pin to sink current (up to 12 mA), effectively pulling it low.
INT_PENDING – This read-only register reects the combined state of the INT_ID0 through
INT_ID2 registers. When any of the lower three bits are set, it indicates that an interrupt is
pending on the I/O port corresponding to the bit position(s) that are set. Reading this register
allows an Interrupt Service Routine to quickly determine if any interrupts are pending and which
I/O port has a pending interrupt.
PAGE/LOCK – This register serves two purposes. The upper two bits select the register page in
use as shown here:
Bits 5-0 allow for locking the I/O ports. A 1 written to the I/O port position will prohibit further
writes to the corresponding I/O port.
I/O Address
Offset Page 0 Page 1 Page 2 Page 3
00H Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O
01H Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O
02H Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O
03H Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O
04H Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O
05H Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O
06H Int_ Pending Int_ Pending Int_ Pending Int_ Pending
07H Page/Lock Page/Lock Page/Lock Page/Lock
08H N/A Pol_0 Enab_0 Int_ID0
09H N/A Pol_1 Enab_1 Int_ID1
0AH N/A Pol_2 Enab_2 Int_ID2
D7 D6 Page
0 0 Page 0
0 1 Page 1
1 0 Page 2
1 1 Page 3
Software Summary
110425 OPERATIONS MANUAL PCM-UIO48B 6
POL0 - POL2 – These registers are accessible when Page 1 is selected. They allow interrupt
polarity selection on a port–by–port and bit-by-bit basis. Writing a 1 to a bit position selects the
rising edge detection interrupts while writing a 0 to a bit position selects falling edge detection
interrupts.
ENAB0 - ENAB2 – These registers are accessible when Page 2 is selected. They allow for port-by-
port and bit-by-bit enabling of the edge detection interrupts. When set to a 1the edge detection
interrupt is enabled for the corresponding port and bit. When cleared to 0, the bit’s edge detection
interrupt is disabled. Note that this register can be used to individually clear a pending interrupt
by disabling and re-enabling the pending interrupt.
INT_ID0 – INT_ID2 – These registers are accessible when Page 3 is selected. They are used to
identify currently pending edge interrupts. A bit when read as a 1 indicates that an edge of the
polarity programmed into the corresponding polarity register has been recognized. Note that a
write to this register (value ignored) clears ALL of the pending interrupts in this register.
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