Wolfson WM8738 Manuale di istruzioni
wWM8738 EV1M
WM8738 Evaluation Board User Handbook
WOLFSON MICROELECTRONICS LTD
www.wolfsonmicro.com
August 2002, Rev 2.1
Copyright 2002 Wolfson Microelectronics Ltd.
INTRODUCTION
The WM8738 is a 24-bit Stereo ADC.
This evaluation platform and documentation should be used in conjunction with the latest version of
the WM8738 datasheet. The datasheet gives device functionality information as well as timing and
data format requirements.
This evaluation platform has been designed to allow the user ease of use and give optimum
performance in device measurement.
GETTING STARTED
PACKING LIST
The WM8738 Evaluation Kit Contains:
•1 WM8738-EV1B Evaluation Board
•This manual -1 WM8738-EV1M
CUSTOMER REQUIREMENTS
Minimum Customer Requires:
•D.C. Power supply of +5V
•D.C. Power supply of +3.0V to +5.5V
•D.C. Power supply of +3.0V to +3.6V
•D.C. Power supply of +12V and -12V
ADC Signal Path Requires (minimum):
•Analogue coaxial jack plug data source
•Digital coaxial data receiving unit
•Master Clock source
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WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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POWER SUPPLIES
Using appropriate power leads with 4mm connectors, +5V should be applied to the +5V panel socket
J1.
+3.0V to +3.6V should be applied to the DVDD panel socket J3 and +3.0V to +5.5V should be
applied to the AVDD panel socket J5.
+12V should be applied to the +12V panel socket J7 and -12V should be applied to the -12V panel
socket J10.
DGND should be connected to the DGND panel socket J2 and AGND to the AGND panel socket J6.
The DGND and AGND connections may be connected to a common GND on the supply with no
reduction in performance.
Note: Refer to WM8738 datasheet for limitations on individual supply voltages.
BOARD FUNCTIONALITY
There are three options for inputting the required digital clocks to the WM8738 evaluation board.
There is a coaxial input (J14) via a standard phono connector or a direct digital input is available via
one side of a 2x6 pin header (H1). A further option is to input a MCLK via connector J9 and use the
CPLD (U1) to generate BCLK and LRCLK.
The analogue input signals are applied to the evaluation board via phono connectors through either
passive or active anti-alias filters. For passive filtering J17 (LIN) and J16 (RIN) can be used and for
active filtering J12 (LIN) and J13 (RIN).
There are two options for outputting digital data from the WM8738 evaluation board. There is a
coaxial output (J8) via a standard phono connector or the digital signals output from the WM8738
may be accessed via one side of a 2x6 pin header (H2).
All WM8738 device pins are accessible for easy measurement via the 8 pin headers (J11 & J15)
running up each side of the device.
BOARD INPUT
Analogue input to the WM8738 is selectable via switches SW5 and SW6. This allows the analogue
input to either pass through a passive anti-aliasing filter, using J17 (LIN) and JI6 (RIN), or an active
anti-aliasing filter, using J12 (LIN) and J13 (RIN).
Digital clock signals must be supplied to the WM8738. A digital (AES/EBU, UEC958, S/PDIF, EIAJ
CP340/1201) signal input may be applied to the coaxial input (J14), allowing the CS8427 (U3) to
generate the necessary clocks. A direct digital input is also available via one side of a 2x6 pin
header (H1). There is also the facility to generate multi-rate clocks from U1 using SW7 as the rate
selection and either the MCLK from the CS8427 (U3) or an independent MCLK input to SMB
connector J9.
The digital inputs of the WM8738 are +5V tolerant (independent of supplies), however, a level shift IC
(U2) has been included in the audio interface signal path to buffer the input signals when applied via
header (H1) and minimise any performance degradation this may cause..
Note: The level shift IC's (U2 and U6) are set to shift from +5V to DVDD when shipped from Wolfson.
BOARD OUTPUT
The output interface from the board is via a coaxial (J8) digital (AES/EBU, UEC958, S/PDIF, EIAJ
CP340/1201) signal output. A direct signal output is available via one side of a 2x6 pin header (H2).
Data is output in one of the WM8738 supported formats - see datasheet.
A level shift IC (U6) has been included in the audio output interface path to provide signal buffering
when output signals are taken from 2x6 pin header H2 will meet external receiver requirements.
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WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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INTERFACES
KEY
1
2
3
4
5
6
7
8
1
2
3
H1
SW1
SW2
1
3
5
7
9
11
2
4
6
8
10
12
J11
J15
J5
J1 J2 J3
H2
J6 J7
J10
1
1
1
1
SW6
SW5
1
SW4
1SW3
1
1SW9
SW8
123456
OPEN
0
1
ON
1234
0
1
SW7
J9
Figure 1 Interfaces
HEADERS
H1 SIGNAL J15 WM8738 SIGNAL
1/2 MCLK
1 1 DVDD
3/4 GND
2 2 SDOUT
5/6 SLAVE_LRC 3 3 BCLK
7/8 GND
4 4 FMT
9/10 SLAVE_BCLK 5 5 CAP
11/12 GND
6 6 VREF
7 7 RIN
H
2 SIGNAL 8 10 AGND
12/11 GND
10/9 SDOUT J11 WM8738 SIGNAL
8/7 GND 1 8 LIN
6/5 BCLK_OUT 2 9 AVDD
4/3 GND 3 10 AGND
2/1 ADC_LRCLK 4 11 NOHP
5 12 LRCLK
6 13 MCLK
7 14 DGND
8 14 DGND
Table 1 Headers
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WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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LINKS
LINKS & JUMPERS DESCRIPTION
SW3
(FMT) Pins 1 & 2 SHORT – Left Justified mode
Pins 2 & 3 SHORT – I2S mode
SW4
(NOHP) Pins 1 & 2 SHORT – Digital HPF Disabled
Pins 2 & 3 SHORT – Digital HPF Enabled
SW5 Pins 1 & 2 SHORT – Active anti-alias filter input selected
Pins 2 & 3 SHORT – RC filter only selected
SW6 Pins 1 & 2 SHORT – Active anti-alias filter input selected
Pins 2 & 3 SHORT – RC filter only selected
SW8 Pins 1 & 2 SHORT – Standard CS8427 BCLK selected
Pins 2 & 3 SHORT – Multi-rate BCLK selected
SW9 Pins 1 & 2 SHORT – Standard CS8427 LRCLK selected
Pins 2 & 3 SHORT – Multi-rate LRCLK selected
J9 External multi-rate MCLK input
Table 2 Links
SWITCHES
SWITCH DESCRIPTION
SW1
(DATA FORMAT)
6 5 4 3 2 1 DATA FORMAT
0 0 1 0 0 1 I2S Compatible
0 0 0 0 0 1 Left Justified
SW2 The CS8427 may be RESET by pressing and releasing switch SW2. This is
required if the switches on SW1 are changed after the board is powered up.
SW7
(MCLK RATE)
4 3 2 1 MCLK RATE
1 0 0 0 256fs
0 1 0 0 384fs
0 0 1 0 512fs
0 0 0 1 768fs
Table 3 Switches
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WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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WM8738 OPERATION
STANDARD CONTROL & USING MULTI-RATE MCLK
The WM8738 is a hardware control only device and must be dealt with as a slave (i.e. all clocks must
be supplied to the WM8738 from another source).
There are only 2 pins that can be used to change the setup of the WM8738, these are pin 4 (FMT)
and pin 11 (NOHP). 3 pin link switch SW3 is used to control the FMT pin, putting this switch high
(short pins 1 & 2) will set the output data format from the WM8738 to Left Justified mode while
putting the switch low (short pins 2 & 3) will set the output data format to I2S mode. 3 pin link switch
SW4 is used to control the NOHP pin, putting this switch high (short pins 1 & 2) will disable the
internal digital High Pass Filter while putting the switch low (short pins 2 & 3) will enable the internal
digital High Pass Filter.
Figure 2shows the basic ‘getting started’ setup required to operate the board. In this example the
data format is set to I2S with the digital HPF set active.
H1
SW1
SW2
J11
J15
J5
J1 J2 J3
H2
J6 J7
J10
1
1
1
1
SW6
SW5
1
SW4
1
SW3
1
1
SW9
SW8
123456
OPEN
0
1
ON
12 34
0
1
SW7
J9
LIN
RIN
SPDIF_
IN
SPDIF_
OUT
+5V DGND
DVDD
+3.0V
to
+3.6V AGND
AVDD
+3.0V
to
+5.5V
+12V
-12V
LIN
RIN
J18
J14
J17
J16
J13
J12
(required to
provideWM8738
Clocks)
Figure 2 Basic Setup Example
LINKS & JUMPERS DESCRIPTION
H1 All Links ON
H2 All Links ON
SW3 (FMT) Pins 2 & 3 SHORT – I2S mode
SW4 (NOHP) Pins 2 & 3 SHORT – Digital HPF Enabled
SW5 Pins 1 & 2 SHORT – Active anti-alias filter input selected
SW6 Pins 1 & 2 SHORT – Active anti-alias filter input selected
SW8 Pins 1 & 2 SHORT – Standard CS8427 BCLK selected
SW9 Pins 1 & 2 SHORT – Standard CS8427 LRCLK selected
Table 4 Basic Setup Example Settings
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WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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An additional feature that has been provided on the WM8738 evaluation board is the ability to run
with multi-rate MCLK’s. This is achieved through the use of the CPLD (U1) and the relevant switch
setting of SW7. Four MCLK rates are supported, 256fs, 384fs, 512fs and 768fs. To operate the
evaluation board in this mode, 3 pin jumper switches SW8 and SW9 should be set so that pins 2 and
3 are shorted, an external MCLK should be supplied through the SMB connector J9, the MCLK is
then passed through the CPLD which divides it down to generate the equivalent LRCLK and BCLK
frequencies.
Figure 3 shows the setup required if using an external MCLK. In this example the data format is set
to I2S digital HPF is active and the MCLK is running at 512fs.
H1
SW1
SW2
J11
J15
J5
J1 J2 J3
H2
J6 J7
J10
1
1
1
1
SW6
SW5
1
SW4
1SW3
1
1SW9
SW8
12 3456
OPEN
0
1
ON
12 34
0
1
SW7
J9
LIN
RIN
+5V DGND
DVDD
+3.0V
to
+3.6V AGND
AVDD
+3.0V
to
+5.5V
+12V
-12V
MCLK
SPDIF_
IN
SPDIF_
OUT
OUT
LIN
RIN
J18
J14
J17
J16
J13
J12
Figure 3 Using an External MCLK Example
LINKS & JUMPERS DESCRIPTION
H1 All Links OFF
H2 All Links ON
SW3
(FMT) Pins 2 & 3 SHORT – I2S mode
SW4
(NOHP) Pins 2 & 3 SHORT – Digital HPF Enabled
SW5 Pins 1 & 2 SHORT – Active anti-alias filter input selected
SW6 Pins 1 & 2 SHORT – Active anti-alias filter input selected
SW8 Pins 2 & 3 SHORT – Multi-rate BCLK selected
SW9 Pins 2 & 3 SHORT – Multi-rate LRCLK selected
J9 External multi-rate MCLK input
Table 5 Using an External MCLK Example Settings
WM8738-EV1M
WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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WM8738-EV1B SCHEMATIC
Figure 4 Functional Diagram
Figure 5 Digital Interface
WM8738-EV1M
WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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Figure 6 Analogue Input
Figure 7 Level Shift / Buffer
WM8738-EV1M
WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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Figure 8 Multi-Rate Generator
Figure 9 WM8738
WM8738-EV1M
WOLFSON MICROELECTONICS LTD Rev 2.1 August 2002
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Figure 10 Power
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