Analog Devices ADSP-TS101 TigerSHARC Guida all'applicazione

ADSP-TS101 TigerSHARC®Processor

Hardware Reference

Revision 1.1, May 2004

Part Number

82-001996-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

ts_101_hwr.book Page i Friday, May 21, 2004 1:29 PM

ii ADSP-TS101 TigerSHARC Processor

Hardware Reference

ment may not be reproduced in any form without prior, express written

consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without

prior notice. Information furnished by Analog Devices is believed to be

accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use; nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by impli-

cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, EZ-ICE, SHARC, TigerSHARC, and the

TigerSHARC logo are registered trademarks of Analog Devices, Inc.

VisualDSP++, Static Superscalar, and EZ-KIT Lite are trademarks of

Analog Devices, Inc.

All other brand and product names are trademarks or service marks of

their respective owners.

ts_101_hwr.book Page ii Friday, May 21, 2004 1:29 PM

ADSP-TS101 TigerSHARC Processor iii

Hardware Reference

CONTENTS

PREFACE

Purpose of This Manual ................................................................. xix

Intended Audience ......................................................................... xix

Manual Contents ............................................................................ xx

Additional Literature ..................................................................... xxii

What’s New in This Manual .......................................................... xxii

Technical or Customer Support ..................................................... xxii

Processor Family ......................................................................... xxiii

Product Information ................................................................... xxiii

DSP Product Information ...................................................... xxiii

Product Related Documents ................................................... xxiv

Technical Publications Online or on the Web .......................... xxiv

Printed Manuals ...................................................................... xxv

VisualDSP++ and Tools Manuals ......................................... xxv

Hardware Manuals ............................................................. xxvi

Data Sheets ........................................................................ xxvi

ts_101_hwr.book Page iii Friday, May 21, 2004 1:29 PM

iv ADSP-TS101 TigerSHARC Processor

Hardware Reference

Recommendations for Improving Our Documents .................. xxvi

Conventions ............................................................................... xxvii

INTRODUCTION

DSP Architecture ......................................................................... 1-6

Compute Blocks ..................................................................... 1-8

Arithmetic Logic Unit (ALU) .............................................. 1-9

Multiply Accumulator (Multiplier) .................................... 1-11

Bit Wise Barrel Shifter (Shifter) ........................................ 1-11

Integer Arithmetic Logic Unit (IALU) ................................... 1-12

Program Sequencer ............................................................... 1-13

Quad Instruction Execution .............................................. 1-14

Relative Addresses for Relocation ...................................... 1-15

Nested Call and Interrupt ................................................. 1-15

Context Switching ............................................................ 1-15

Internal Memory and Other Internal Peripherals .................... 1-16

Internal Buses ................................................................... 1-16

Internal Transfer ............................................................... 1-17

Data Accesses ................................................................... 1-17

Quad Data Access ............................................................. 1-17

Scalability and Multiprocessing ............................................. 1-18

External Port ......................................................................... 1-19

External Bus and Host Interface ........................................ 1-19

External Memory .......................................................... 1-19

Multiprocessing ............................................................ 1-20

ts_101_hwr.book Page iv Friday, May 21, 2004 1:29 PM

ADSP-TS101 TigerSHARC Processor v

Hardware Reference

Host Interface ............................................................... 1-21

DMA Controller ............................................................... 1-22

Link Ports ......................................................................... 1-23

Miscellaneous ........................................................................ 1-23

Timers .............................................................................. 1-23

Clock Domains ................................................................. 1-23

Booting ...................................................................................... 1-24

Emulation and Test Support ........................................................ 1-24

Programming Model ................................................................... 1-25

MEMORY AND REGISTER MAP

Memory Access Features ................................................................ 2-1

Host Address Space ................................................................. 2-2

External Memory Bank Space .................................................. 2-4

Multiprocessor Space ............................................................... 2-5

Internal Address Space ............................................................. 2-6

Internal Memory Access ........................................................... 2-7

Broadcast Write .................................................................. 2-8

Merged Distribution ........................................................... 2-8

Broadcast Distribution ........................................................ 2-8

Data Alignment Buffer ............................................................ 2-9

Compute Block Register Files ................................................ 2-10

Merged Access .................................................................. 2-11

ts_101_hwr.book Page v Friday, May 21, 2004 1:29 PM

vi ADSP-TS101 TigerSHARC Processor

Hardware Reference

Broadcast Transfer ............................................................ 2-11

Unmapped Compute Block Registers ................................ 2-12

Global Registers—XSTAT/YSTAT

Compute Block Status Registers ................................. 2-13

ALU Registers .............................................................. 2-13

Multiplier Registers ...................................................... 2-13

Shifter Registers ............................................................ 2-13

Communications Logic Unit (CLU) Registers ............... 2-13

IALU Registers ...................................................................... 2-14

Sequencer Register Groups .................................................... 2-15

Sequencer Control Register – SQCTL ............................... 2-16

Sequencer Control Register Set Bits – SQCTLST .............. 2-16

Sequencer Control Register Clear Bits – SQCTLCL .......... 2-16

Sequencer Status Register – SQSTAT ................................ 2-16

SFREG Register ............................................................... 2-16

ILAT Registers .................................................................. 2-19

IMASK Register ............................................................... 2-19

PMASK Register ............................................................... 2-19

Interrupt Vector Table Register Groups ............................. 2-20

Debug Register Groups ......................................................... 2-21

Performance Monitor Counter – PRFCNT ....................... 2-23

Performance Monitor Mask – PRFM ................................ 2-23

Watchpoint Control – WP0CTL, WP1CTL and WP2CTL 2-25

ts_101_hwr.book Page vi Friday, May 21, 2004 1:29 PM

ADSP-TS101 TigerSHARC Processor vii

Hardware Reference

Watchpoint Status – WP0STAT, WP1STAT and WP2STAT 2-27

Cycle Counters – CCNT0 and CCNT1 ............................ 2-29

Trace Buffer – TRCB0 to TRCB7 and TRCBPTR ............. 2-29

Watchpoint Address Pointers – WP0L, WP1L, WP2L, WP0H,

WP1H and WP2H ......................................................... 2-29

External Port Registers ........................................................... 2-30

Bus Control/Status (BIU) Register Group .......................... 2-30

SYSTAT/SYSTATCL Register ........................................ 2-31

SYSCON Register (DMA 0x180480) ............................ 2-34

SDRCON (SDRAM Configuration) (DMA 0x180484) . 2-36

BUSLK System Control ................................................ 2-38

BMAX Current Value .................................................... 2-39

BMAX Register ............................................................. 2-39

External Port Configuration and Status Registers ............... 2-41

DMA Registers ................................................................. 2-41

External Port DMA Register .......................................... 2-43

AutoDMA Registers ...................................................... 2-43

AutoDMA0 Register ..................................................... 2-44

AutoDMA1Register ...................................................... 2-44

Link Port Transmit DMA Register ................................. 2-45

Link Port Receive DMA Register ................................... 2-45

DMA Control and Status Register ................................. 2-46

Link Registers ................................................................... 2-47

Link Port Control and Status Register ............................ 2-47

Link Port Receive and Transmit Buffers ......................... 2-48

ts_101_hwr.book Page vii Friday, May 21, 2004 1:29 PM

viii ADSP-TS101 TigerSHARC Processor

Hardware Reference

CORE CONTROLS

Clock Inputs ................................................................................ 3-1

Operation Modes ......................................................................... 3-2

Emulation Mode ..................................................................... 3-3

Supervisor Mode ..................................................................... 3-4

User Mode .............................................................................. 3-5

Low Power Mode .......................................................................... 3-6

Entering Low Power Mode ...................................................... 3-6

Single Processor System ...................................................... 3-6

Multiprocessing Systems ..................................................... 3-7

Return to Normal Operation ................................................... 3-8

Flag Pins ...................................................................................... 3-8

Timers ......................................................................................... 3-9

Timer Registers ....................................................................... 3-9

Timer Operations ................................................................... 3-9

Timer 0 Output Pin .............................................................. 3-10

INTERRUPTS

Interrupt I/O Pins ........................................................................ 4-2

Interrupt Vector Table .................................................................. 4-2

Interrupt Types ............................................................................. 4-3

Level or Edge Interrupts .......................................................... 4-3

Interrupts Generated by On-Chip Modules ................................... 4-4

Timers .................................................................................... 4-4

ts_101_hwr.book Page viii Friday, May 21, 2004 1:29 PM

ADSP-TS101 TigerSHARC Processor ix

Hardware Reference

Link Interrupts ........................................................................ 4-5

DMA Interrupts ...................................................................... 4-5

Interrupt Pins (IRQ) ............................................................... 4-6

Vector Interrupt (VIRPT) ........................................................ 4-7

Bus Lock Interrupt .................................................................. 4-7

Hardware Error Operations ..................................................... 4-8

Software Exceptions ...................................................................... 4-9

Emulation Debug .................................................................. 4-10

Other Interrupt Registers ............................................................ 4-11

ILAT Register ........................................................................ 4-11

IMASK Register .................................................................... 4-12

PMASK Register ................................................................... 4-13

Interrupt Service ......................................................................... 4-14

Interrupt Handling ................................................................ 4-19

Returning From Interrupt ........................................................... 4-22

Exceptions .................................................................................. 4-23

CLUSTER BUS

External Bus Features .................................................................... 5-2

Bus Interface I/O Pins ................................................................... 5-3

Processor Microarchitecture ........................................................... 5-3

SYSCON Programming .............................................................. 5-11

Bus Width ............................................................................. 5-14

Slow Device Protocol ............................................................. 5-14

Pipelined Protocol ................................................................. 5-15

ts_101_hwr.book Page ix Friday, May 21, 2004 1:29 PM

x ADSP-TS101 TigerSHARC Processor

Hardware Reference

Initial Value .......................................................................... 5-15

TigerSHARC Pipelined Interface ................................................ 5-15

Control Signals ..................................................................... 5-16

Basic Transaction .................................................................. 5-16

Pipelining Transactions ......................................................... 5-18

Wait Cycles ........................................................................... 5-23

Slow Device Protocol .................................................................. 5-27

EPROM Interface ....................................................................... 5-31

Flyby Transactions ...................................................................... 5-34

Multiprocessing .......................................................................... 5-38

Bus Arbitration Protocol ....................................................... 5-41

Core Priority Access (CPA) ............................................... 5-43

DMA Priority Access (DPA) ............................................. 5-43

Bus Fairness — BMAX ..................................................... 5-47

Bus Lock .......................................................................... 5-47

Host Interface ....................................................................... 5-48

Backoff ............................................................................. 5-50

SDRAM INTERFACE

SDRAM I/O Pins ......................................................................... 6-7

SDRAM Physical Connection ....................................................... 6-8

Internal TigerSHARC processor Address and SDRAM Physical

Connection ........................................................................ 6-11

SDRAM Programming ............................................................... 6-19

SDRAM Control Register (SDRCON) .................................. 6-19

ts_101_hwr.book Page x Friday, May 21, 2004 1:29 PM

Indice

Altri manuali Analog Devices Hardware per computer

Analog Devices

Analog Devices ADSST-EM-3040 Manuale utente

Analog Devices

Analog Devices Blackfin Manuale utente

Analog Devices

Analog Devices LTM4683 Manuale utente

Analog Devices

Analog Devices DC2745A Guida rapida alla configurazione

Analog Devices

Analog Devices VisualDSP++ 5.0 Manuale utente

Analog Devices

Analog Devices AD73360L Manuale utente

Analog Devices

Analog Devices ADM1060 Manuale utente

Analog Devices

Analog Devices ADM1060 Manuale utente

Analog Devices

Analog Devices AD9843A Manuale utente

Analog Devices

Analog Devices EZ-Board ADSP-21489 Manuale utente

Analog Devices

Analog Devices Linear LT3383 Guida rapida alla configurazione

Analog Devices

Analog Devices ADSP-CM419F Manuale utente

Analog Devices

Analog Devices DC3089A Manuale utente

Analog Devices

Analog Devices EZ-KIT Lite ADSP-BF537 Manuale utente

Analog Devices

Analog Devices Blackfin Manuale utente

Analog Devices

Analog Devices LTC6955 Guida rapida alla configurazione

Analog Devices

Analog Devices EZ-KIT Lite ADSP-BF537 Manuale utente

Analog Devices

Analog Devices EVAL-AD7606SDZ Manuale utente

Analog Devices

Analog Devices EVAL-ADG5401FEBZ Manuale utente

Analog Devices

Analog Devices MicroConverter ADuC824 Manuale utente

Analog Devices

Analog Devices Linear LTC3114-1 Guida rapida alla configurazione

Analog Devices

Analog Devices ADSP-CM411F Manuale utente

Analog Devices

Analog Devices EVAL-ADPD6000 Manuale utente

Analog Devices

Analog Devices SHARC ADSP-21368 Guida all'applicazione

Manuali Hardware per computer popolari di altre marche

EMC2

EMC2 VNX Series Manuale del proprietario

Panasonic

Panasonic DV0PM20105 Manuale utente

Mitsubishi Electric

Mitsubishi Electric Q81BD-J61BT11 Manuale utente

Gigabyte

Gigabyte B660M DS3H AX DDR4 Manuale utente

Raidon

Raidon iT2300 Manuale utente

National Instruments

National Instruments PXI-8186 Manuale utente

Hauppauge

Hauppauge WinTV-HVR-2250 Manuale utente

Kontron

Kontron CP6002 Manuale utente

Manhattan

Manhattan 702843 Manuale utente

Aphex

Aphex 230 Manuale utente

AMD

AMD Phenom II Manuale operativo

Intel

Intel NUC 12 Pro Manuale utente

dbx

dbx Zone Pro 1260 Manuale utente

Galaxy

Galaxy GHDX2-2430S-24F4D Manuale utente

Intel

Intel AXXRMFBU4 Manuale utente

Kontron

Kontron DIMM-PC/MD Manuale utente

ST X-NUCLEO-SAFEA1B Istruzioni operative

STEINWAY LYNGDORF

STEINWAY LYNGDORF SP-1 Manuale utente