EMAC IPac HCS12 Manuale utente

iPac HCS12

Users Manual

EMAC, Inc.

2390 EMAC, Way

Carbondale, IL 62902

Phone: (618) 529-4525

Fax: (618) 457-0110

http://www.emacinc.com

iPac HCS12 Manual.doc -1 -Rev 1.2 -11/11/03

iPac HCS12 Users Manual rev1.2

Table of Contents

1. Introduction..........................................................................................................................................................................2

1.1 Features........................................................................................................................................................................2

1.2 Options.........................................................................................................................................................................2

1.3 Other Options...............................................................................................................................................................3

2. Hardware..............................................................................................................................................................................3

2.1 Specifications...............................................................................................................................................................3

2.2 Jumpers........................................................................................................................................................................3

2.3 JTAG & BDM..............................................................................................................................................................4

2.4 Processor Based Multi-Purpose Digital I/O.................................................................................................................5

2.5 PLD Based General Purpose Digital I/O......................................................................................................................6

2.6 Analog Channels..........................................................................................................................................................7

2.7 RS232 SERIAL 0 UART.............................................................................................................................................8

2.8 RS 232/422/485 SERIAL 1 UART..............................................................................................................................8

2.9 CAN I/O.......................................................................................................................................................................9

2.10 LCD .............................................................................................................................................................................9

2.11 Keypad.......................................................................................................................................................................10

2.12 Real Time Clock (RTC).............................................................................................................................................10

3. Software.............................................................................................................................................................................11

3.1 Introduction................................................................................................................................................................11

3.2 Bootloader..................................................................................................................................................................11

4. PCD-39E00 Terminal Board..............................................................................................................................................12

4.1 Introduction................................................................................................................................................................12

4.2 iPac Terminal Board Pinout.......................................................................................................................................12

iPac HCS12 Manual.doc -2 -Rev 1.2 -11/11/03

1. Introduction

This document describes EMAC’s iPac HCS12 Single Board Computer (SBC) module. The iPac HCS12 is a PC/104 SBC

sized module that provides a wide variety of I/O. Controlled by Motorola’s powerful HCS12 processor this module provides

maximum flexibility with ample processing speed for most control applications. Although being extremely powerful with

ample I/O for demanding applications, this board consumes minimal power, is low cost, and has a small footprint. The iPac

HCS12 uses the Standard PC/104 form factor (3.8" x 3.5") allowing the use of standard PC/104 mounting hardware and

enclosures. The features of the iPac HCS12 are as follows:

1.1 Features

§CPU: Motorola 68HCS12 16 Bit Processor running with a CPU clock speed of about 50 MHz with BDM debugger

capability.

§MEMORY: 128K of internal Flash in-circuit programmable, 2K byte EEPROM, 8K of RAM, and 96 bytes of

battery backed RAM.

§DIGITAL I/O: 16 General Purpose HCS12 Digital I/O lines, 8 Digital Inputs, 8 Digital Outputs, and 8 High Drive

Digital Outputs..

§COUNTER/PWM: 8 Multi-Purpose HCS12 Digital I/O lines (GP/Counters/PWM).

§ANALOG INPUTS: 16 channels of 10 bit A/D 0 -5 volts.

§ANALOG OUTPUTS: 2 channels of 8 bit D/A using filtered PWM channels.

§COMMUNICATION: 1 RS232 Port and 1 RS232/422/485 port.

§TIME: Battery Backed Real Time Clock/Calendar.

§RESET: External Reset Button provision.

§INTERFACES: Character LCD interface with backlight support and a 24 key, keypad interface.

•FORM FACTOR: PC/104 Module with Dimensions of 96 mm x 90 mm (3.77" x 3.54").

1.2 Options

ON-BOARD OPTIONS

•ANALOG: Analog I/O Upgrade Includes:

•8 additional channels of 12 bit A/D, 0 -5 Volts or 4 to 20 ma. input provision.

•4 additional channels of 12 bit D/A, 0 -5 Volts.

•CAN: An Optically Isolated CAN 2.0 A, B Port.

•SOFTWARE: MODBUS slave capability.

iPac HCS12 Manual.doc -3 -Rev 1.2 -11/11/03

1.3 Other Options

•TERMINAL BOARD: Screw Terminal Board allows for easy access to the iPac HCS12 I/O. Up to two Screw

Terminal Boards can be stacked onto a single iPac HCS12.

2. Hardware

2.1 Specifications

§VOLTAGE REQUIREMENTS: Onboard regulation allows 5 volt or 7.5 -15 volt DC board input voltage.

§CURRENT REQUIREMENTS: 120 ma. @ 5 Volts Typical

§OPERATING TEMPERATURE: 0 -70 degrees Centigrade, humidity range without condensation 0% to 90%

RH.

§DIGITAL I/O: 16 programmable General Purpose TTL level I/O lines with an output drive capability of 10 ma. 8

Multipurpose TTL level I/O lines with an output drive capability of 10 ma. and a maximum total I/O drive of 50 ma.

for these 24 lines. These lines can also be configured as Counters inputs and PWM outputs. 8 dedicated Digital

Inputs and 8 dedicated Digital Outputs with 25 ma. drive capability. 8 open collector High-Drive Digital outputs

with 500 ma. sink drive capability and a maximum total I/O drive of 1500 ma. for these 8 lines. All Digital I/O lines

terminate to standard 50 pin, I/O Rack compatible header connectors.

§ANALOG INPUTS: 8 analog inputs are multiplexed into a two 10-bit A/D converters with Sample & Hold for a

total of 16 channels with a conversion time of 7 usec. The analog input voltage range for each channel is 0 -5 Volts.

An optional 12-bit, 8 channel A/D is available bringing the analog input total to 24 channels.

§ANALOG OUTPUTS: 2 independent analog outputs implemented using 2 hardware 8-bit filtered PWM channels.

The analog output voltage range for each output is 0 -5 Volts with a drive capability of 5 ma. An optional 12-bit, 4

channel D/A is available bringing the analog output total to 6 channels.

2.2 Jumpers

This section describes the Jumpers and Jumper Blocks of the iPac HCS12.

2.2.3 JP1

LCD Config. LCD configuration jumpers. These Jumpers allow for different types of LCDs and backlight control.

Jumper AB1 &AB2 backlight always on

Jumper BC1 &AB2 port line control (PK7 –LCDBKL) of backlight through software

Jumper BC1 &BC2 allows the use of certain graphic LCDs

2.2.4 JP2

CAN Term. Place a jumper in the T position to terminate the CAN bus.

iPac HCS12 Manual.doc -4 -Rev 1.2 -11/11/03

2.2.5 JP3

Serial1 Config This jumper determines which interface Serial Port 1 utilizes. Place the jumper in the 232 position for use

as an RS 232 port and place the jumper in the 422 position for use as a RS 422/485 interface.

2.2.6 JB1

4 –20 ma. This jumper block allows the selection of any of the optional 12 bit A/D inputs to utilize 4 –20 ma. inputs

instead of 0 –5 volt inputs. Simply jumper the appropriate channel(s) to allow 4 –20 ma. inputs. Each

jumper position has the channel number designated next to it.

2.2.7 JB2

VIN+ Config This jumper block selects the iPac’s input voltage requirements. JB2 configures VIN+ to be a direct 5V

connection or a 9-14V connection. Setting this jumper incorrectly can damage the board. The two possible

configurations are as follows.

VIN+ = 9-14 Volts regulated on board (default). Both jumpers are in the V+ position.

2 –4

1 –3

VIN+ = 5V Direct voltage (no regulation). Both jumpers are in the 5 position.

4 –6

3 –5

2.3 JTAG & BDM

This multipurpose header provides a programming interface to the PLD which translates the bus signals as well as a

debugging interface directly to the Processor. Currently it is only used internally be EMAC.

Table 1: JTAG & BDM Interface (HDR10)

Signal

JTAG_TCK

GND

JTAG_TDO

5V (Vcc)

JTAG_TMS

CPU_RESET

NC/Reserved

BKGND

JTAG_TDI

GND

iPac HCS12 Manual.doc -5 -Rev 1.2 -11/11/03

2.4 Processor Based Multi-Purpose Digital I/O

These GPIO lines are exactly that, general purpose. They are connected directly to the processor, so use caution when

interfacing to these lines. The names of each line listed in Table 2 matches the port line on HCS 12 processor.

When used as outputs these lines can drive 10 ma. and when used as inputs the input voltage should not exceed 5 Vdc.

Besides being bit configurable I/O lines they can also be used as PWMs, and PT lines can be used as 16 bit counters. For

software purposes PT is referred to as GP port 0, and PP is GP port 1.

Table 2: PROCESSOR BASED DIGITAL I/O Connector (HDR3)

Signal

PH3

GND

PH2

GND

PP5

GND

PP4

GND

PP3

GND

PP2

GND

PP1

GND

PP0

GND

PT7

GND

PT6

GND

PT5

GND

PT4

GND

PT3

GND

PT2

GND

PT1

GND

PT0

GND

PA7

GND

PA6

GND

PA5

GND

PA4

GND

PA3

GND

PA2

GND

PA1

GND

PA0

GND

5V(Vcc)

GND

iPac HCS12 Manual.doc -6 -Rev 1.2 -11/11/03

2.5 PLD Based General Purpose Digital I/O

These input and output lines provide connections for heavier industrial relays and switches. They are connected to the PLD

of the iPac HCS12 with the exception of lines PE0 –PE4 which are connected directly to the processor. These 5 lines with

the addition of PZ0 –PZ2 make up a dedicated input port whose input lines should not exceed 5 Vdc. The dedicated output

port lines PY0 –PY7 can drive 25 ma. loads. The open collector high drive output port PX0 –PX7 has drive 500 ma. sink

drive capability and a maximum total I/O drive of 1500 ma. for these 8 lines.

Table 3: PLD BASED DIGITAL I/O Connector (HDR1)

Signal

PY7

GND

PY6

GND

PY5

GND

PY4

GND

PY3

GND

PY2

GND

PY1

GND

PY0

GND

PX7

GND

PX6

GND

PX5

GND

PX4

GND

PX3

GND

PX2

GND

PX1

GND

PX0

GND

PZ2

GND

PZ1

GND

PZ0

GND

PE4

GND

PE3

GND

PE2

GND

PE1

GND

PE0

GND

5V(Vcc)

GND

The PLD is connected to the HCS12 processor using pseudo data bus comprised of the processor’s port lines. Table 4 defines

these port line assignments. To access PLD Port X, perform a write with A0 = 0. To access PLD Port Y, perform a write with

A0 = 1. To access PLD Port Z, perform a read with A0 = 0.

Table 4: PLD PSUEDO DATA BUS PORT LINE ASSIGNMENTS

ocessor Port Line

Description

Processor Port Line

Description

PB0

DBUS 0

PJ0

DBUS A0

PB1

DBUS 1

PJ1

R/*W

PB2

DBUS 2

PJ7

PLD *CS

PB3

DBUS 3

PB4

DBUS 4

PB5

DBUS 5

PB6

DBUS 6

PB7

DBUS 7

iPac HCS12 Manual.doc -7 -Rev 1.2 -11/11/03

2.6 Analog Channels

The HC12 coprocessor on the iPac HCS12 provides two independent 10 bit 8 port A/D modules. These modules provide

lines ANI00 -ANI15. In addition to the A/D, the iPac HCS12 provides 2 D/A channels that are implemented by filtering two,

8-bit hardware PWM channels PP6 & PP7. An 8 channel, 12 bit A/D and/or a 4 channel, 12 bit D/A is available optionally.

These optional analog channels are provided through external SPI devices. The A/D input channel except 0 –5 Volt inputs.

The optional 12 bit A/D in addition to the 0 –5 Volt inputs can be jumpered using JB1 to 5 –20 ma. All D/A channels

provide 0 –5 Volt outputs with a drive capability of 5 ma.

Table 5: ANALOG (HDR2)

Signal

ANI00

2ANI01

ANI02

ANI03

ANI04

ANI05

ANI06

ANI05

ANI08

ANI09

ANI10

ANI11

ANI12

ANI13

ANI14

ANI15

GND

DAC00

DAC01

GND

DAC02

DAC03

DAC04

DAC05

GND

ANI16

ANI17

ANI18

ANI19

ANI20

ANI21

ANI22

ANI23

GND

5V(Vcc)

+VIN

In order to access the optional 12 bit A/D (LTC1290) and D/A (TLV5614) communication must take place using HCS12’s

SPI. Table 6 details these processor connection to both the 12 A/D and D/A.

Table 6: OPTIONAL A/D & D/A PORT LINE ASSIGNMENTS

Processor Port Line

Description

Processor Port Line

Description

PS4

MISI

PK3

A/D *CS

PS5

MOSI

PK4

D/A *CS

PS6

SCLK

PK5

*LDAC

iPac HCS12 Manual.doc -8 -Rev 1.2 -11/11/03

2.7 RS232 SERIAL 0 UART

The iPac HCS12 provides one dedicated RS232 UART Serial 0 which has software configurable baud rates. Both

transmission and asynchronous data reception are possible. Handshake Lines are implemented by the use of port lines PH0

and PK0.

Table 7: RS232 (HDR8)

Signal

DB9 Description

TxD

RxD

CTS (PH0)

RxD

GND

RTS (PK0)

CTS (PH0)

RTS (PK0)

GND

2.8 RS 232/422/485 SERIAL 1 UART

The iPac HCS12 provides one jumper (JP 3) selectable RS 232/422/485 UART which has software configurable baud rates.

Both transmission and asynchronous data reception are possible. RS232 Handshake Lines are implemented by the use of PH1

and PK1. When using this serial port in the RS422/485 mode, Handshake Line PK1 controls the transmitter enable line of the

RS422/485 driver.

Table 8: RS485 (HDR9)

Signal

DB9 Description

RS422/485 TX-

RS422/485 TX

RS232 TXD or 422/485 TX+

RS232 RXD or 422/485 RX+

CTS (PH1)

RS422/485 RX

RS232 RXD or 422/485 RX+

GND

RTS (PK1)

RS422/485 RX-

CTS (PH1)

RTS (PK1)

GND

iPac HCS12 Manual.doc -9 -Rev 1.2 -11/11/03

2.9 CAN I/O

The iPac HCS12 provides a single optically coupled CAN bus with 2 connectors (in & out). The CAN bus is provided by the

processor CAN port which is available on port lines PM0 & PM1. Jumpering JP 2 enables the terminating resistor for end of

network termination.

Table 9: CAN (HDR4)

Signal

DB9 Description

CANL

GND

CANH

GND

CANH

Table 10: CAN (HDR5)

Signal

DB9 Description

CANL

GND

CANH

GND

CANH

2.10 LCD

This header currently supports 2 and 4 line, character LCDs.

Table 11: LCD Interface (HDR6)

Signal

VCC

GND

CNTR

R/W*

K (JP1 Pin3)

A (JP1 Pin4)

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