Freescale Semiconductor M54455EVB Manuale utente

Freescale Semiconductor

User’s Manual M54455EVBUM

Rev. 4, 01/2008

Contents

1 Introduction

1.1 Purpose

This document provides design and usage information

for the Freescale M54455EVB evaluation, development

and reference platform.

The M54455EVB platform provides an evaluation

system for the Freescale MCF5445xColdFire®V4m

embedded microprocessor family. The MCF54455 is the

superset device in the family and is the processor

featured on this platform. This allows evaluation and

development for the entire family on a single hardware

platform.

1.2 Related Documents

• MCF54455 Reference Manual

• M54455EVB Quick Start Guide

• M54455EVB Schematics

• MC34702 Switch-Mode with Linear Power

Supply Datasheet

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 MCF54455 Overview. . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 M54455EVB Overview . . . . . . . . . . . . . . . . . . . . . . 4

2.3 Memory Map Overview . . . . . . . . . . . . . . . . . . . . . . 6

2.4 I/O Back Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . 7

4 Hardware Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.1 DDR SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Reset Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3 MCF5445xBoot Options. . . . . . . . . . . . . . . . . . . . . 9

4.4 System Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.5 SPI Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.6 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.7 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.8 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.9 BDM and JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.10 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.11 Ethernet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.12 ATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.13 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.14 CPLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.15 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.16 Serial Interface Header . . . . . . . . . . . . . . . . . . . . . 33

4.17 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.18 Logic Analyzer Connections . . . . . . . . . . . . . . . . . 35

4.19 Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.20 Jumpers, Headers, and Switches . . . . . . . . . . . . . 35

5 U-Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

M54455EVB User’s Manual

by: Microcontroller Solutions Group

M54455EVB User’s Manual, Rev. 4

2Freescale Semiconductor

• Universal Serial Bus Specification, Revision 2.0

• PCI Local Bus Specification, Revision 2.2

• DDR2 SDRAM Specification (JESD79-2C)

2 Overview

2.1 MCF54455 Overview

The MCF54455 is the host processor for the M54455EVB. Figure 1 shows a top-level block diagram of

the MCF54455 superset device. The following is a brief summary of the functional blocks in the

MCF54455 superset device.

• Version 4 ColdFire Core with MMU and EMAC

— Up to 410 Dhrystone 2.1 MIPS @ 266 MHz

• 16 KBytes instruction cache and 16 KBytes data cache

• 32 Kbytes internal SRAM

• Support for booting from SPI-compatible flash, EEPROM, and FRAM devices

• Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus

masters

• 16 channel DMA controller

• 16-bit 133MHz DDR/mobile-DDR/DDR2 Controller

• USB 2.0 On-the-Go controller with ULPI support

• 32-bit PCI controller @ 66MHz

• ATA/ATAPI controller

• Two 10/100 Fast Ethernet Controllers (FECn)

• Cryptographic acceleration unit (CAU)

• Random number generator

• Synchronous serial interface

• Four periodic interrupt timers

• Four 32-bit timers with DMA support

• DMA-supported serial peripheral interface (DSPI)

• Three UARTs

•I

2C bus interface

M54455EVB User’s Manual, Rev. 4

Freescale Semiconductor 3

Figure 1. MCF54455 Block Diagram

Version 4 ColdFire Core

LEGEND

2 INTCs

DSPI

EPORT

3 UARTs

I2C

Watchdog

4 DMA

RTC

ATA – Advanced Technology Attachment Controller

BDM – Background debug module

CAU – Cryptography acceleration unit

DSPI – DMA serial peripheral interface

eDMA – Enhanced direct memory access

EMAC – Enhanced multiply-accumulate unit

EPORT – Edge port module

FEC – Fast Ethernet Controller

GPIO – General Purpose Input/Output

I2C– Inter-Integrated Circuit

INTC – Interrupt controller

JTAG – Joint Test Action Group interface

MMU – Memory management unit

PCI – Peripheral Component Interconnect

PIT – Programmable interrupt timers

PLL – Phase locked loop module

RNG – Random Number Generator

RTC – Real time clock

SSI – Synchronous Serial Interface

USB OTG – Universal Serial Bus On-the-Go controller

MCF54455

EMAC 2 FECs

Crossbar Switch (XBS)

32K

SRAM

Peripheral Bridge

CAU

16K

Instruction

Cache

16K

Data

Cache

Timers

BDM

ATA SDRAM

Controller FlexBus

eDMA

USB OTG

4 PITs

SSI RNG GPIO

MMU

Hardware

Divide

Oscillator PLLJTAG

PCI Serial Boot

M54455EVB User’s Manual, Rev. 4

4Freescale Semiconductor

2.2 M54455EVB Overview

The M54455EVB provides hardware to evaluate as many of the configurations of the MCF5445xfamily

as possible. The M54455EVB features:

• Freescale MCF54455 ColdFire microprocessor

• DDR2 SDRAM (256 MByte)

• Two NOR flash memory devices (16 MByte, 512 KByte)

• Serial flash

• MRAM (512 KByte, accessible through FPGA Flexbus interface)

• Four PCI slots (32-bit, for MCF5445xas a PCI host system)

• Two-port Ethernet interface

• 40-pin ATA connector

• Audio interface (I2S mode of SSI module connected to audio codec)

• Multiple USB interface options

— FS/LS Host via on-chip transceiver with host support (Type A receptacle)

— HS/FS/LS dual-role via external ULPI PHY (Mini-AB receptacle)

• Two RS232 serial ports (RS232 transceivers on UART0 & UART1)

• One USB serial port (UART0 serial converted to USB converted on UART0)

• Built-in P&E Micro USB Multilink debug interface

• Standard 26-pin BDM header

• Serial interface header for access to timers, interrupts, DSPI, I2C, and more

• Clock generation logic adjustable via I2C

• LEDs and 7-segment display programmable via CPLD and FPGA

• Low-profile, micro-ATX computer case with built-in power supply

Figure 2. M54455EVB Kit

M54455EVB User’s Manual, Rev. 4

Freescale Semiconductor 5

Figure 3. M54455EVB Block Diagram

ColdFire

MCF5445x

SDRAM Bus

DDR2 Term Reg

0.9V VTT 0.9V VREF

MC34702

1.5V3.3V 1.8V

ATX Power Supply

Barrel Pwr

Connector

MC34702

1.2V

3.3V 1.8V

CPLD

512K Flash

8-bit data bus

Flash0

16MB Flash

8-bit data bus

Flash1

FPGA

MRAM

Buffered Flexbus

PCI Slot 0

3.3V PCI Bus

PCI Slot 1

PCI Slot 2

PCI Slot 3

PCI Clock Buffer Programmable Clock

Generator

EXTAL

PCI Arbi Cntrl and

Interrupts

Interfaces for RS232,

RS232-to-USB, DSPI, I2C,

Timers, etc.

SSI Audio

Interface USB Full-

speed

Interface

USB ULPI

Interface

ULPI

Dual FEC PHY (RMII

mode) and 2xRJ45 w/

integrated magnetics and

LEDs

FEC0RMII

FEC1 RMII / ATA_DATA[8:15]

ATA

ATA_DATA[15:8]

ATA_DATA[7:0], Control

Serial I/O,

Interrupts,

Timers, etc.

DDR2 Parallel Termination

VTTVREF

DDR2

4 x 512Kbit (64M8)

Serial Flash

Reset

Configuration

Latch

BDM & JTAG 26-pin Connector

Boot Mode

Selection

Compression Logic

Analyzer Connectors

surrounding processor for

access to all switching

signals

PCI Arbitration and Interrupts

Chip Selects

CPLD Switchable Options

Clocks for FPGA, Eth PHY, USB

ATA Buffer

ATA_DATA[15:8]

FlexBus

M54455EVB User’s Manual, Rev. 4

6Freescale Semiconductor

2.3 Memory Map Overview

Figure 1 illustrates the overall memory map for the MCF54455 and M54455EVB.

Much of the memory map is dictated by the MCF5445xmemory map. Refer to the “Overview” and

“Crossbar Switch” sections of the MCF54455 Reference Manual for more details.

Table 1. M54455EVB Memory Map

Function Start Address End Address Size

Flexbus—Flash1 0x0000_0000 0x00FF_FFFF 16 MB

Flexbus—Flash0 0x0400_0000 0x0407_FFFF 512 KB

Flexbus—CPLD1

1The CPLD and FPGA sections contain details on the memory-mapped registers within

these address spaces.

0x0800_0000 0x08FF_FFFF 16 MB

Flexbus—FPGA/MRAM10x0900_0000 0x09FF_FFFF 16 MB

DDR2 SDRAM 0x4000_0000 0x4FFF_FFFF 256 MB

MCF5445xInternal SRAM 0x8000_0000 0x8000_7FFF 32 KB

ATA 0x9000_0000 0x9FFF_FFFF 256 MB

PCI 0xA000_0000 0xBFFF_FFFF 512 MB

Flexbus—Unused 0xC000_0000 0xDFFF_FFFF 512 MB

Reserved 0xE000_0000 0xEFFF_FFFF 256 MB

Internal Peripheral Space 0xF000_0000 0xFFFF_FFFF 256 MB

M54455EVB User’s Manual, Rev. 4

Freescale Semiconductor 7

2.4 I/O Back Panel

Refer to Figure 4 for the I/O back panel descriptions.

Figure 4. M54455EVB I/O Back Panel Port Locations

3 Installation and Configuration

The M54455EVB comes pre-programmed with U-Boot and Linux pre-configured to run a demo

application. This section describes how to setup the evaluation board to access the bootloader to start

Linux.

The default communication interface with the M54455EVB is a simple serial port console. A terminal

emulator on a host PC and the supplied serial cable is required to interact with the serial port. Alternately,

a USB cable can be used if the USB serial port is configured for use (refer to Section 4.17, “Serial Ports”

for details).

The basic installation steps are as follows:

1. Plug in the case’s power supply with the power cable provided.

2. Connect one end of the provided serial cable to the DB9 serial port connector labelled UART0

(Refer to Figure 4).

3. Connect the other end of the serial cable to a free DB9 serial port connector on a host PC.

4. Open the terminal emulator of your choice (e.g. HyperTerminal, Tera Term, minicom, etc.).

USB Serial Port

FS/LS USB Host

HS/FS/LS USB Dual-role

Serial Ports:

Top = UART0

Bottom = UART1

Audio Interface:

Blue = Line-in

Green = Line-out

Pink = Mic

Ethernetl Ports:

Top = FEC1

Bottom = FEC0

USB BDM interface

M54455EVB User’s Manual, Rev. 4

8Freescale Semiconductor

5. Configure the COM port as follows:

6. Press the power switch on the front of the computer case and the U-Boot banner (example below)

should appear in the terminal window.

U-Boot 1.2.0-g4a442d31-dirty (Aug 23 2007 - 11:14:19)

CPU: Freescale MCF54455 (Mask:48 Version:1)

CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 33 Mhz

INP CLK 33 Mhz VCO CLK 533 Mhz

Board: Freescale M54455 EVB

I2C: ready

DRAM: 256 MB

FLASH: 16.5 MB

In: serial

Out: serial

Err: serial

Net: FEC0, FEC1

IDE: Bus 0: not available Status = 0x60

Linux and a root file system are preprogrammed into the second Flash device (Flash1) at address

0x0000_0000. A demo application automatically runs when Linux is started. A network

connection is required for the web server portion of the demo to work.

7. Plug one end of the provided Ethernet cable into a network or host PC with a DHCP server running.

Plug the other end of the cable into the FEC0 interface (bottom RJ45 receptacle) of the

M54455EVB.

8. To boot Linux, issue the following U-Boot command.

-> bootm 0

9. The demo application prints out a banner message including the IP address that it obtained from

the DHCP server. Launch a web client (e.g. Firefox or Internet Explorer) and copy this IP address

into the web browser. The M54455EVB serves up a web page with more information on the

available demos.

4 Hardware Submodules

The following sections describe the hardware submodules of the M54455EVB.

Table 2. Default Serial Console Settings

Parameter Setting

Baud Rate 115,200 bps

Data bits 8

Parity None

Stop bits 1

Flow Control None or Software (Xon/Xoff)

M54455EVB User’s Manual, Rev. 4

Freescale Semiconductor 9

4.1 DDR SDRAM Interface

The MCF5445xDDR SDRAM controller has the following features:

• Supports a glueless interface to DDR, DDR2, and mobile/low-power DDR SDRAM devices

• Support for 16-bit fixed memory port width

• 16-byte critical word first burst transfer

• Up to 14 lines of row address, up to 11 column address lines, 2 bits of bank address, and two chip

selects.

• Supports up to 512 MByte of memory; minimum memory configuration of 8 MByte

• Supports page mode to maximize the data rate

• Supports sleep mode and self-refresh mode

The M54455EVB features 256 MBytes of DDR2 SDRAM. Four 8-bit wide Micron MT47H64M8

(512 Mbit) devices are arranged as two 16 M ×8 ×4 banks per SDRAM controller chip select. This results

in two 16-bit wide, 128 MBytes blocks of DDR2 memory

The SDRAM interface is terminated with parallel termination resistors. The MCF5445xdoes not provide

control for the DDR2 on-die termination. The ODT pins on the DDR2 devices are connected to control

signals from the CPLD for test purposes only. These signals are disabled in the normal functional mode.

4.2 Reset Controller

The reset controller on the M54455EVB is implemented in a Xilinx XC95144XL CPLD. The CPLD

controlsthestate of the system reset signal(SYSRESET)gathers reset information from a pushbutton reset

(SW2), the BDM interface, and the FPGA (FPGA_DONE). At system power-on, the CPLD holds

SYSRESET asserted until the FPGA has loaded its image from the platform flash PROM and asserted the

FPGA_DONE signal. After system power-on, the CPLD asserts SYSRESET when it detects the assertion

of any of the reset sources.

4.3 MCF5445xBoot Options

During a system reset, the CPLD also drives the boot mode configuration signals into the MCF5445x. The

MCF5445xhas three boot mode options:

• Boot with default configuration constants specified in the RCON register,

• Boot with configuration data specified by the Flexbus FB_AD[7:0] pins, and

• Boot with configuration data obtained from an external SPI memory through the serial boot

facility.

In all of these cases, the boot code is fetched from an external memory connected to the Flexbus on

FB_CS0 with the possible exception of the serial boot mode. In serial boot mode, if the boot load length

field (BLL) in the reset configuration data stored in the SPI memory is non-zero, then boot code is loaded

from the SPI memory instead of from Flexbus.

The MCF5445xboot mode is determined by the state of the BOOTMOD[1:0] input pins during the rising

edge of RSTOUT (MCF5445xreset output signal). The CPLD drives BOOTMOD[1:0] to the values that

M54455EVB User’s Manual, Rev. 4

10 Freescale Semiconductor

are set on the CPLD mode signals (CPLD_MODE[1:0]). The CPLD_MODE signals are set by the CPLD

configuration switch, SW1. See Section 4.14, “CPLD” for more details. Table 3 shows the SW1 settings

and their corresponding boot mode configurations.

4.3.1 Default Configuration (SW1[2:1] = ON:ON)

If the BOOTMOD pins are 00 during reset, the MCF5445xRCON register determines the chip

configuration after reset, regardless of the states of the external data pins. The RCON register specifies the

following default configuration for the MCF54455:

• PCI enabled, muxed Flexbus address/data, 8-bit port-size boot

• PLL enabled

• PCI host mode

• 66MHz PCI slew rate mode

• PLL multiplier: fVCO = 6 ×fREF

4.3.2 Parallel Configuration (SW1[2:1] = OFF:ON)

If the BOOTMOD pins are 10 during reset, the MCF5445xconfiguration after reset is determined

according to the levels driven onto the FB_AD[7:0] pins. On the M54455EVB, the FB_AD[7:0] pins are

actively driven by an 8-bit buffer enabled when the MCF5445xRSTOUT signal is asserted. The values

driven by the buffer are set by the SW3 DIP switch settings. Refer to Table 4 for the configuration setting

information.

Table 3. M54455EVB Boot Mode Selection

BOOTMOD[1:0] SW1[2:1] Meaning

00 ON:ON Boot from Flexbus with defaults (from RCON register)

01 ON:OFF Reserved

10 OFF:ON Boot from Flexbus and override defaults via data bus (FB_AD[7:0])

11 OFF:OFF Boot from Flexbus and override defaults via serial boot facility (SPI memory)

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