JYTEK PXIe-69529 Manuale utente

PXIe-69529

8-CH 24-Bit 204.8 kS/s

Dynamic Signal Acquisition Module

User’s Manual

Manual Rev.: 1.00

Revision Date: Jul.16,2016

Getting Service

SHANGHAI JYTEK Co., Ltd.

Web site: hp://www.jytek.com

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203

China

Tel: +86-21-5047-5899

Fax: +86-21-5047-5899

Email: [email protected]

Addional informaon, aids, and ps that help users perform tasks

Informaon to prevent minor physical injury, component damage, data loss,

and/or program corrupon when trying to complete a task.

Informaon to prevent serious physical injury, component damage, data loss,and/

or program corrupon when trying to complete a specic task.

Table of Contents

Geng Service �� I

1 Introducon�� 1

1�1 Features �� 1

1.2 Applicaons �� 1

1.3 Specicaons �� 2

1�3�1 Analog Input �� 2

1�3�2 Timebase �� 4

1�3�3 Triggers �� 4

1.3.4 General Specicaons �� 4

1.4 Soware Support �� 5

1�4�1 SDK �� 5

1�4�2 DSA-DASK�� 5

1�5 Device Layout and I/O Array�� 6

2 Geng Started�� 8

2.1 Installaon Environment �� 8

2�2 Installing the Module �� 9

3 Operaons ��10

3.1 Funconal Block Diagram��10

3�2 Analog Input Channel��10

3.2.1 Analog Input Front-End Conguraon ��10

3�2�2 Input Range and Data Format��11

3�2�3 ADC and Analog Input Filter ��12

3�2�4 DMA Data Transfer��12

3�3 Trigger Source and Trigger Modes��14

3�4 Trigger Mode��16

3�5 ADC Timing Control ��18

3�5�1 Timebase ��18

3�5�2 DDS Timing vs� ADC��18

3�5�3 Filter Delay in ADC ��19

3.6 Synchronizing Mulple Modules ��19

3.6.1 SSI_TIMEBASE ��20

3�6�2 SSI_SYNC_START ��20

3�6�3 SSI_TRIG��20

Appendix A Calibraon ��21

A.1 Calibraon Constant ��21

A.2 Auto-Calibraon ��21

Important Safety Instrucons ��22

III

List of Tables

Table 1-1: Channel Characteriscs�� 2

Table 1-2: Timebase�� 4

Table 1-3: Trigger Source & Mode �� 4

Table 1-4: Digital Trigger Input �� 4

Table 3-1: Input Range and Data Format ��11

Table 3-2: Input Range Midscale Values ��12

Table 3-3: ADC Sample Rates vs DDS Output Clock��12

Table 3-4: Preferred Characteriscs for Analog Triggers��16

Table 3-5: Timing Relaonship between ADC and PLL Clock ��18

Table 3-6: ADC Filter Delay��19

Table 3-7: SSI Timing Signal Denions ��19

List of Figures

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp �� 3

Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp �� 3

Figure 1-3: PXIe-69529 schemac �� 6

Figure 1-4: PXIe-69529 I/O Array�� 7

Figure 3-1: Analog Input Architecture ��10

Figure 3-2: Linked List of PCI Address DMA Descriptors��13

Figure 3-3: Trigger Architecture��14

Figure 3-4: External Digital Trigger ��14

Figure 3-5: Analog Trigger Condions ��16

Figure 3-6: Post-Trigger Acquision��17

Figure 3-7: Delay Trigger Mode Acquision��17

Figure 3-8: Re-Trigger Mode Acquision ��18

Figure 3-9: Timebase Architecture ��18

Figure 3-10: SSI Architecture��20

1 Introduction

The PXIe-69529 is a high-performance 8-CH 24-Bit 204.8 kS/s dynamic signal acquision

module, specically designed for applicaons such as structural health monitoring, noise,

vibraon, and harshness (NVH) measurement, and phased array data acquision.

The PXIe-69529 features 24-bit simultaneous sampling at 204.8 kS/s over 8 channels,

and a 110 dB dynamic range, providing ample power for high-density, high channel count

signal measurement, and vibraon-opmized lower AC cuto frequency of 0.3 Hz. All input

channels incorporate 4 mA bias current for integrated electronic piezoelectric (IEPE) signal

condioning for accelerometers and microphones.

The PXIe-69529 is auto-calibrated with an onboard reference circuit calibrang oset and

acquiring analog input errors. Following auto-calibraon, the calibraon constant is stored

in EEPROM, such that these values can be loaded and used as needed by the board. There

is no requirement to calibrate the module manually.

1�1 Features

• PXI Express specicaon Rev. 1.0 compliant

• 8 simultaneous analog inputs

• 204.8 kS/s maximum sampling rate

• AC or DC input coupling, soware selectable

• Support for:

◦ One external digital trigger input

◦ IEPE output on each analog input, soware congurable

◦ Auto-calibraon

1�2 Applications

• Structural health monitoring

• Phase array data acquision

• Noise, vibraon, and harshness (NVH) detecon

• Machine status monitoring

1�3 Specifications

1�3�1 Analog Input

Channel Characteriscs Comment

Channels 8

Type Dierenal or Pseudo-Dierenal

Coupling AC or DC, soware selectable

AC coupling cuto frequency 0.5Hz

ADC resoluon 24-Bit

ADC type Delta-sigma

Input signal range ±10V, ±1V

Sampling rate (fs) 8 kS/s to 204.8 kS/s,

768 μS/s increments for fs > 108 kS/s,

576 μS/s increments for 54 kS/s ≤ fs

≤108 kS/s

Over voltage protecon Dierenal: ±42.4V, Pseudo-

dierenal:

• posive terminal ±42.4 V

• negave terminal unprotected,

rated at ±2.5 V

Input impedance 1MΩ, (50Ω between negave input and

system ground for pseudo-dierenal

mode)

Oset error ±1 mV max.

Gain error ±0.1% of FSR

SNR, @n = 1kHz 103 dB fs = 8.0 kS

104 dB fs = 54.0 kS

99 dB fs = 108 kS

98 dB fs = 192 kS

THD < -106 dB

SFDR > 106 dB

crosstalk < -100 dB

-3 dB bandwidth >0.4863 fs fs < 108 kS

≌ 0.2 fs fs > 108 kS

IEPE

Current 4 mA, each channel independently

soware congurable

Compliance 24V

Table 1-1: Channel Characteriscs

0 1 2 3 4 5 6

x 10

−25

−20

−15

−10

−5

Magnitude Response

Frequency (Hz)

Magnitude (dB)

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp

0 1 2 3 4 5 6 7 8 9 10

−12

−10

−8

−6

−4

−2

0Response when AC coupling enabled

Frequency (Hz)

Magnitude (dB)

Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp

1�3�2 Timebase

Sampling Clock

Timebase opons Internal: onboard synthesizer

External: PXI_CLK10, PXIe_CLK100

Timebase accuracy < ± 25ppm

Table 1-2: Timebase

1�3�3 Triggers

Trigger Source & Mode

Trigger source Soware, external digital trigger, analog trigger, PXI trigger

bus[0..7], PXI_STAR, and PXIe_DSTARB

Trigger mode Post trigger and delay trigger

Table 1-3: Trigger Source & Mode

Digital Trigger Input

Sources Front panel SMA connector

Compability 3.3 V TTL, 5 V tolerant

Input high threshold 2.0 V

Input low threshold (VIL) 0.8 V

Maximum input overload -0.5 V to +5.5 V

Trigger polarity Rising or falling edge

Pulse width 20 ns minimum

Table 1-4: Digital Trigger Input

1�3�4 General Specifications

Physical

Physical dimensions 160 W x 100 H mm (6.24 x 3.9 in)

Bus

Bus interface PCI Express Gen1 x 4

Environmental Tolerance

Operang Temperature: 0°C - 55°C

Relave humidity: 10% - 90%, non-condensing

Storage Temperature: -20°C - +80°C

Relave humidity: 10% - 90%, non-condensing

Calibraon

Onboard reference +5.000 V

Temperature coecient < 5.0 ppm/°C

Warm-up me 15 minutes

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