Lattice Semiconductor XP2 Advanced Manuale utente

March 2011

Revision: EB30_01.5

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LatticeXP2 Advanced Evaluation Board



User’s Guide

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

Introduction

The LatticeXP2™ Advanced Evaluation Board provides a convenient platform to evaluate, test and debug user

designs and IP cores targeted for the LatticeXP2-17 FPGA. The board features of a LatticeXP2-17 FPGA in a 484

fpBGA package. The LatticeXP2 I/Os are connected to a rich variety of both generic and application-specific inter-

faces described later in this document.

Important: This document (including the schematics in the appendix) describes LatticeXP2 Advanced Evaluation

Boards marked as Rev B. This marking can be seen on the silkscreen of the printed circuit board, under the Lattice

Semiconductor logo.

The LatticeXP2 is a second-generation non-volatile FPGA device. It combines a Look-up Table (LUT) based FPGA

fabric with Flash non-volatile cells in a flexiFLASH™ architecture. The flexiFLASH approach provides benefits such

as instant-on, small footprint, on chip storage with FlashBAK™ embedded block memories and Serial TAG memory

and design security. The LatticeXP2 also support live updates with TransFR™, 128-bit AES encryption and dual-

boot technologies. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase

Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP™ blocks.

For a full description of the LatticeXP2 FPGA, see the Lattice website for data sheets, technical notes, technology

summaries and more: www.latticesemi.com.

Some common uses for the LatticeXP2 Advanced Evaluation Board include:

• Video and other DSP processing

• An analog-to-digital, and digital-to-analog mixed signal source/sink

• A single-board computer system

• A platform for evaluating the Input/Output (I/O) characteristics of the FPGA

• A platform for evaluation and development with Lattice IP cores

Features

Key features of the LatticeXP2 Advanced Evaluation Board include:

• SPI Serial Flash device included for low-cost, non-volatile configuration storage

• One 32-bit DDR2 SO-DIMM module connector

• 32-bit PCI connector

• Both a Tri-speed (10/100/1000 Mbit) Ethernet PHY that includes RJ-45, magnetics and spark gap, as well as a

directly wired RJ-45 connector

• RS-232 interface chip and 9-pin D-sub connector

• PS/2 Mouse connector

• USB 1.1 transceiver and USB type-A and type-B connectors

• USB download of LatticeXP2 and power manager bitstreams

• Video TX and RX MDR connectors

• Quad 12-bit ADC and Quad 12-bit DAC

• Two 8-pin DIP switches

• Discrete LEDs and 7-segment LED

• CompactFlash connector for type I and type II CompactFlash cards

• LCD module connector

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

• Prototyping areas with access to 14 I/O pins

• Selectable I/O bank voltages

• Four pairs of SMA connectors for high speed differential signals

• Oscillator socket for both half-size and full-size oscillators

• 3.3V, 2.5V, 1.8V, 1.2V and ADJ (adjustable voltage) powers generated from a single 5V to 28V power source

•ispPAC

®-POWR1220AT8 Power Manager II device for monitoring the 3.3V, 2.5V, 1.8V, 1.2V, ADJ voltages and

DDR Vref, Vtt voltages

•ispVM

®System programming support

General Description

The heart of the board is the LatticeXP2 non-volatile FPGA. The board also provides several different interconnec-

tions and support devices that permit it to be used for a variety of purposes. The PCI connector, DDR2 socket, and

Tri-speed Ethernet PHY are useful for applications using Lattice IP cores.

A number of connectors are useful for general purpose of the LatticeXP2 I/O capability. These include the SMA

connectors, RS-232, Video Tx/Rx MDR connectors, and the various generic prototype access points.

The CompactFlash connector is also useful for expansion purposes. It provides the ability to add storage, or com-

munication capabilities to the board.

Other features on the board help in evaluating the capabilities and performance of the LatticeXP2. The A/D, D/A,

and digital potentiometer are helpful for some basic mixed signal applications. The SMA connectors permit the

evaluation of high-speed differential signals, and protocols. The SPI memory showcases the failsafe capabilities of

the LatticeXP2.

The board also acts as a showcase for the ispPAC-POWR1220 power manager. The ispPAC-POWR1220 is a pro-

grammable device useful for safely managing the power supply system on the board. While the LatticeXP2 device

has no specific power-sequencing requirements, the ispPAC-POWR1220 device can be used to sequence and

monitor voltages.

Additional Resources

Additional resources for the LatticeXP2 Advanced Evaluation Board, such as updates to this document, sample

programs and links to demos can be found on the Lattice web site. Go to www.latticesemi.com/boards, and navi-

gate to the appropriate page for this board.

Initial Setup and Handling

The following is recommended reading prior to removing the evaluation board from the static shielding bag and

may or may not apply to your particular use of the board.

CAUTION: The devices on the board can be damaged by improper handling.

The devices on the evaluation board contain fairly robust ESD (Electro Static Discharge) protection structures

within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example

of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their

designed in protection. For example: higher static voltages, as well as lower voltages with lower series resistance

or larger capacitance than the respective ESD specifications require can potentially damage or degrade the

devices on the evaluation board.

As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while han-

dling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for a

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

while, it’s best to put it back in the static shielding bag. Please save the static shielding bag and packing box for

future storage of the board when it is not in use.

When reaching for the board, it is recommended that you first touch the outside threaded portion of one of the gold

SMA connectors. This will neutralize any static voltage difference between your body and the board prior to any

contact with signal I/O.

CAUTION: to minimize the possibility of ESD damage, the first and last electrical connection to the board, should

always be from test equipment chassis ground to GND on the board (black banana jack).

Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment

to the GND on the board. Connecting the board ground to test equipment chassis ground will decrease the risk of

ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when unplugging

cables from the evaluation board, the last connection unplugged, should be the chassis GND connection to eval

board GND. If you have signal sources that are floating with respect to chassis GND, attempt to neutralize any

static charge on that signal source prior to attaching it to the evaluation board.

If you are holding or carrying the board while it’s not in a static shielding bag, please keep one finger on the

threaded portion of one of the gold SMA connectors. This will keep the board at the same voltage potential as your

body until you can pick up the static shielding bag and put the board back in it.

Electrical, Mechanical, and Environmental Specifications

The nominal board dimensions are 12 inches by 6 inches. The environmental specifications are as follows:

• Operating temperature: 0°C to 55°C

•Storage temperature: -40°C to 75°C

• Humidity: <95% without condensation

• 5V to 28V DC (20 watts max.)

Functional Description

Figure 1. LatticeXP2 Advanced Evaluation Board

8-Position

Switch

CompactFlash

DDR2 SO-DIMM

LatticeXP2

FPGA

MachXO2280

32-Bit PCI Edge

Video MDR

Tx/Rx

USB

Programming

9-Pin D-Sub

RS-232

USB Device/

Host

Generic RJ-45

PS/2 Mouse

8-Position

Switch

On/Off

Switch

ispPAC-POWR

1220AT8

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

LatticeXP2 Device

This board features a LatticeXP2 FPGA with a 1.2V DC core in a 484-ball fpBGA package. The default device is

the LatticeXP2-17. Any other LatticeXP2 density in this package can be accommodated. A complete description of

this device can be found on the Lattice web site at www.latticesemi.com.

Power Setup

The board is supplied by a single 5.0V to 28.0V DC power supply. On-board regulators will provide the necessary

supply voltages. The on-board regulators supply 3.3V, 2.5V, 1.8V, 1.2V, and an adjustable voltage (VCC_ADJ). The

adjustable voltage is set by the potentiometer VR1 and can be set to a value between 1.22V and 3.25V. The DC

power may be applied through the power jack at J54 using an AC adapter with a 5.0V to 28.0V DC output range.

Requirements for the power jack are listed in Ta b l e 1. The on/off switch (SW9) can be used as a convenience to

disable power jack J54. Be sure that SW9 is in the “on” position for normal operation.

The DC power may also be applied using a workbench power supply through the banana jacks at J53 (VCC_IN)

and J51 (GND). The workbench power supply voltage has to be between 5.0V and 28.0V.

Table 1. Power Jack J54 Specifications

Polarity Positive Center

Inside Diameter 0.1” (2.5mm)

Outside Diameter 0.218” (5.5mm)

Current Capacity Up to 4A

Power may also be supplied directly for each individual supply rail using banana jack connectors. To enable this

mode of operation, the appropriate fuses must be removed. All power sources must be regulated to the specifica-

tions in Table 2. No special power sequencing is required for the evaluation board.

Table 2. Individual Control of Supplies

Supply Jack Fuse Requirement

3.3V J50 F5 (3.0A) +/- 5%

2.5V J41 F1 (3.0A) +/- 5%

1.8V J47 F3 (10.0A) +/- 5%

1.2V J48 F4 (3.0A) +/- 5%

VCC_ADJ J46 F2 (1.5A) User-defined

Power Voltage Monitoring

A Lattice’s ispPAC Power Manager II device, ispPAC-POWR1220AT8, is used for monitoring various voltages on

the board. There are six LEDs used to indicate the status of the monitoring voltages. If the monitoring voltage is not

in the +/- 5% voltage window, the corresponding LED will be flashing, otherwise the LED will stay ON. Tab l e 3

shows these six voltages and the corresponding LEDs.

Table 3. Individual Monitoring of Six Power Voltages

Voltage LED Monitoring Voltage Range

3.3V D5 3.3V +/- 5%

2.5V D6 2.5V +/- 5%

1.8V D7 1.8V +/- 5%

1.2V D8 1.2V +/- 5%

Vref D9 0.9V +/- 5%

Vtt D10 0.9V +/- 5%

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

For the VCC_ADJ adjustable voltage, the ispPAC-POWR1220AT8 will detect the voltage rail and show the status

using five LEDs. Each of these five LEDs indicates a particular voltage range. If the VCC_ADJ is in one of the volt-

age ranges, the corresponding LED will be turned ON and the other LEDs will be turned OFF, otherwise these five

LEDs will be turned ON and then OFF sequentially so that you will see a light keep moving between the LEDs. The

five LEDs and corresponding voltages are listed in Ta bl e 4.

Table 4. Monitoring of VCC_ADJ Power Voltages

LED Indicating Voltage Range

D11 3.3V +/- 5%

D12 2.5V +/- 5%

D13 1.8V +/- 5%

D14 1.5V +/- 5%

D15 1.2V +/- 5%

LatticeXP2 I/O Bank Voltage Setting

The jumpers listed in Ta bl e 5 allow the user to select the voltage (VCCIO) applied to each of the eight I/O banks of

the LatticeXP2 device. Certain restrictions apply depending on which features of the board are being used.

Table 5. VCCIO Selection Jumper

sysIO™ Bank Jumper Jumper on Pins

0J34 1-3 -> VCC_3.3V

2-4 -> VCC_2.5V

3-5 -> VCC_1.8V

4-6 -> VCC_ADJ

6J37

1VCC_2.5V

2VCC_1.8V

3VCC_1.8V

4VCC_3.3V

5VCC_3.3V

7VCC_3.3V

Depending on the optional devices installed, some sysIO banks may have restrictions. For each of J34 and J37

only select one bank voltage position at that jumper. For example, attaching more than one jumper to J34’s 6

square pins will short supplies.

Table 6. sysIO Bank Considerations

Bank Setting

0Selectable. CompactFlash requires 3.3V.

1Cannot be changed

6Selectable. Video TX/RX requires 2.5V.

7Cannot be changed

The following tables detail the various I/O standards supported by the LatticeXP2 sysIO structures. More informa-

tion can be found in technical note TN1136, LatticeXP2 sysIO Usage Guide.

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

Table 7. Mixed Voltage I/O Support

VCCIO

Input sysIO Standards Output sysIO Standards

1.2V 1.5V 1.8V 2.5V 3.3V 1.2V 1.5V 1.8V 2.5V 3.3V

1.2V Ye s Ye s Ye s Ye s

1.5V Ye s Ye s Ye s Ye s Ye s

1.8V Ye s Ye s Ye s Ye s Ye s

2.5V Ye s Ye s Ye s Ye s

3.3V Ye s Ye s Ye s Ye s

For example, if VCCIO is 3.3V then signals from devices powered by 1.2V, 2.5V, or 3.3V can be input and the thresh-

olds will be correct, assuming the user has selected the desired input level using ispLEVER®software. Output lev-

els are tied directly to VCCIO.

Table 8. sysIO Standards Supported per Bank

Description Top Side, Banks 0-1 Right Side, Banks 2-3 Bottom Side, Banks 4-5 Left Side, Banks 6-7

Types of I/O Buffers Single-ended Single-ended and

Differential

Single-ended Single-ended and

Differential

Output standards

supported

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

SSTL18 Class I, II

SSTL25 Class I, II

SSTL33 Class I, II

HSTL15 Class I

HSTL18_I, II

SSTL18D Class I, II

SSTL25D Class I, II

SSTL33D Class I, II

HSTL15D Class I

HSTL18D Class I, II

PCI33

LVDS25 E1

LVPECL1

BLVDS1

RSDS1

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

SSTL18 Class I, II

SSTL25 Class I, II

SSTL33 Class I, II

HSTL15 Class I

HSTL18 Class I, II

SSTL18D Class I, II

SSTL25D Class I, II

SSTL33D Class I, II

HSTL15D Class I, II

HSTL18D Class I, II

PCI33

LVDS

LVDS25 E1

LVPECL1

BLVDS1

RSDS1

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

SSTL18 Class I

SSTL2 Class I, II

SSTL3 Class I, II

HSTL15 Class I

HSTL18 Class I, II

SSTL18D Class I, II

SSTL25D Class I, II,

SSTL33D Class I, II

HSTL15D Class I

HSTL18D Class I, II

PCI33

LVDS25 E1

LVPECL1

BLVDS1

RSDS1

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

SSTL18 Class I

SSTL2 Class I, II

SSTL3 Class I, II

HSTL15 Class I, III

HSTL18 Class I, II, III

SSTL18D Class I,

SSTL25D Class I, II,

SSTL33D_I, II

HSTL15D Class I

HSTL18D Class I, II

PCI33

LVDS

LVDS25 E1

LVPECL1

BLVDS1

RSDS1

Inputs All Single-ended,

Differential

All Single-ended,

Differential

All Single-ended,

Differential

All Single-ended,

Differential

Clock Inputs All Single-ended,

Differential

All Single-ended,

Differential

All Single-ended,

Differential

All Single-ended,

Differential

PCI Support PCI33 no clamp PCI33 no clamp PCI33 with clamp PCI33 no clamp

LVDS Output Buffers LVDS (3.5mA) Buffers2LVDS (3.5mA) Buffers2

1. These differential standards are implemented by using complementary LVCMOS drivers and external resistors.

2. Available on 50% of the I/Os in the bank.

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

Prototype Areas

For general purpose I/O testing or monitoring, numerous test points are provided for direct access. Some test

points are grouped together and arranged in a grid pattern according to their associated I/O bank and are labeled

with the pin locations on the silkscreen of the board. Other test point I/Os are brought out to IDC connectors J1 and

J10 with both source and end termination resistors available for high speed parallel signal transmission over ribbon

cable.

Differential Signal Connections

There are four pairs of SMA connectors and one RJ-45 connector connected directly to the LatticeXP2 differential

I/O pairs.

The eight SMA connectors are provided for clocks or general purpose, user-definable signals. The center pin is

wired to an I/O pin and the outer case is soldered to ground. Ta ble 9 details to which I/O pin each SMA connector

is wired.

Table 9. SMA Connectors

Location LatticeXP2 I/O Polarity sysIO Bank Description

J121A2* Pair#0 P 0PT4A/ULC_GPLLT_IN_A

J6 B3 Pair#0 N 0PT4B/ULC_GPLLC_IN_A

J13 F7 Pair#1 P 0PT5A/ULC_GPLLT_FB_A

J7 G7 Pair#1 N 0PT5B/ULC_GPLLC_FB_A

J14 P4 Pair#2 P 6PL37A

J8 P5 Pair#2 N 6PL37B

J15 Y1 Pair#3 P 6PL35A

J9 AA1 Pair#3 N 6PL35B

1. The SMA connector on J12 is shared with the on-board oscillator. When this SMA connector is used, the jumper on

J17 needs to be removed.

RJ-45 Connectors

There are two RJ-45 connectors, J5 and J43, on the evaluation board. J5 is a simple RJ-45 female connector pro-

vided for general-purpose differential interfacing to the LatticeXP2 device, while J43 is a full featured Ethernet PHY

connection with internal magnetics and spark gap. The connections for J5 are listed in Ta bl e 10. J43 is described in

more detail in the Ethernet section later in this user guide.

Table 10. J5 RJ-45 Connections

J1 Pin LatticeXP2 I/O Polarity SysIO Bank Description

1P2 Pair#0 P 6PL32A

2P3 Pair#0 N 6PL32B

3T1 Pair#1 P 6PL30A/LDQS30

6U1 Pair#1 N 6PL30B

4M4 Pair#2 P 6PL28A

5M5 Pair#2 N 6PL28B

7R5 Pair#3 P 6PL40A

8P6 Pair#3 N 6PL40B

Oscillator

The 3.3V oscillator socket (Y1) accepts both full-size and half-size oscillators and can route to different clock

inputs, depending on its position within the socket (see Figure 2). The board is shipped with an EPSON program-

mable oscillator programmed to 33.33MHz.

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

The 16-pin socket will allow connection to PLL clock pin A2 when the top of the oscillator is aligned to socket pins 1

and 16. Note that the SMA connector J12 is shared with the on-board oscillator. When installing the oscillator to

connect the clock to PLL clock pin A2, the SMA connector J12 cannot be used and the jumper on J17 needs to be

installed.

When the bottom of the oscillator is aligned to socket pins 8 and 9, the clock is provided to primary clock pin L4.

Figure 2. On-board Oscillator

SPI Serial Flash

SPI Serial Flash are available in three package styles. The device used this board is an 8-pin, 16-Mbit, sufficient to

store two bitstreams simultaneously in order to support SPIm mode.

Configuration/Programming Headers

Four programming headers are provided on the evaluation board, providing access to the LatticeXP2, MachXO™,

and ispPAC-POWR1220AT8 and LatticeXP2 SPI Slave JTAG ports. The JTAG connectors J25, J32, J39 and J40

are 1x10 headers. The JTAG ports for the LatticeXP2 and ispPAC-POWR1220AT8 devices can be configured as

loop-through connectors to allow for easy daisy chaining of multiple boards. With proper jumper selection (see the

next section) standard IDC ribbon cable can be used without the need to swap any wires on the cable.

The pinouts for these headers are provided in the following tables.

A USB ispDOWNLOAD®cable is included with each LatticeXP2 Advanced Evaluation Board. When using the 1x8

cable adapter, connect pin 1 of the cable to pin 1 of the 1x10 JTAG header.

Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-

LOAD Cable or USB cable. Always connect an ispDOWNLOAD Cable’s GND pin (black wire), before connecting

any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeXP2 FPGA and ren-

der the board inoperable.

LatticeXP2 Configuration

Two programming headers, J39 and J40, are provided on the evaluation board, providing access to the LatticeXP2

JTAG port and the ispPAC-POWR1220AT8 JTAG port. The pinouts for the headers are provided in Tabl e 11.

LatticeXP2 Advanced

Lattice Semiconductor Evaluation Board User’s Guide

Table 11. JTAG Programming Headers

Separate Programming Chained Programming

Jumper on J49 (None on J45) Jumper on J45 (None on J49)

J39 Function J40 Function J39 Function J40 Function

1Vcc (3.3V) Vcc (3.3V) Vcc (3.3V) Not used

2TDO of ispPAC-POWR1220AT8 TDO of LatticeXP2 TDO of ispPAC-POWR1220AT8 Not used

3TDI of ispPAC-POWR1220AT8 TDI of LatticeXP2 TDI of LatticeXP2 Not used

4NC NC NC Not used

5NC NC NC Not used

6TMS of both chips TMS of both chips TMS of both chips Not used

7GND GND GND Not used

8TCK of ispPAC-POWR1220AT8 TCK of LatticeXP2 TCK of both chips Not used

9NC DONE of LatticeXP2 NC Not used

10 NC INITN of LatticeXP2 NC Not used

J49 and J45 control the functions of the two programming headers. When a jumper is installed on J49, the pro-

gramming header J39 is connected to the JTAG port of ispPAC-POWR1220AT8 and is used for programming the

ispP

AC-POWR1220AT8 only; the programming header J40 is connected to the JTAG port of LatticeXP2 and is

used for programming the LatticeXP2 only.

When the jumper is moved from J49 to J45, the JTAG ports of the LatticeXP2 and ispPAC-POWR1220AT8 are

chained together. In this case, the programming header J40 is connected to the JTAG port of the LatticeXP2 first

and then chained with the JTAG port of ispPAC-POWR1220AT8. The programming header J39 should not be used

when the JTAG ports are chained together. During chained programming, the ispPAC-POWR1220AT8 device will

set the HVOUT1 signal (pin 86 of U17) tri-state until programming completes, so the enable for the 3.3V power for

the LatticeXP2 device will be interrupted during programming unless a jumper is installed at J52. After chained pro-

gramming of the ispPAC-POWR1220AT8, the jumper at J52 can be removed.

Additional instructions and recommendations for programming this board are provided in the Configuring/Program-

ming the Board section of this document.

Switches

There are two 8-position switches and six push-button switches for implementing basic static input functions.

Switches SW3, SW4, SW5, SW6, SW7 and SW10 are momentary switches. The pull-up resistors associated with

these switches are wired to 3.3V. Pushing the switches down produces a low (0), otherwise it produces a high (1).

The signals controlled by SW4, SW5, SW6, SW7 and SW10 are debounced by an MC14490 (U15) before connect-

ing to an LatticeXP2 I/O pin. Ta bl e 12 shows the control relationship between the switches, LatticeXP2 and ispPAC-

POWR1220AT8 I/O pins.

Table 12. Momentary Switches

Switch Connection User-Definable Debounced

SW3 Pin 97 of ispPAC-POWR1220AT8* Ye s 1No

SW4 J6 of LatticeXP2 (PROGRAMN) No Ye s

SW5 E12 of LatticeXP2 (GSRN) Ye s Ye s

SW6 W18 of LatticeXP2 Ye s Ye s

SW7 W17 of LatticeXP2 Ye s Ye s

SW10 U7 of LatticeXP2 Ye s Ye s

1. SW3 signal is also connected (wire-AND) to position#1 of SW2. Therefore, when position#1 of SW2 is in the down position,

SW3 signal (POWR1220AT8 pin 97) will be low even when SW3 is not being pushed.

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