National Instruments 5761R Manuale utente

NI 5761R User Guide and Specifications

The NI 5761 is a 250 MS/s analog input adapter module designed to work in conjunction with your

NI FlexRIO™FPGA module. This document contains signal information and specifications for the

NI 5761R, which is comprised of an NI FlexRIO FPGA module and the NI 5761. This document also

contains tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA example VI

and how to create and run your own LabVIEW project with the NI 5761R.

Contents

Front Panel and Connector Pinouts ..................................................................................................... 2

Block Diagram ..................................................................................................................................... 4

NI 5761 Component-Level Intellectual Property (CLIP) .................................................................... 5

Cables................................................................................................................................................... 6

Clocking............................................................................................................................................... 7

Using Your NI 5761R with a LabVIEW FPGA Example VI.............................................................. 7

Creating a LabVIEW Project and Run a VI on an FPGA Target ........................................................ 9

How to Use Your NI FlexRIO Documentation Set ............................................................................. 12

Specifications....................................................................................................................................... 13

Where to Go for Support ..................................................................................................................... 24

Note Before configuring your NI 5761R, you must install the appropriate software and hardware.

Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation

instructions. Figure 1 shows an example of a properly connected NI FlexRIO device.

Figure 1. NI FlexRIO Device

NI FlexRIO

Adapter Module + = NI FlexRIO Device

NI FlexRIO

FPGA Module

NI 5761R User Guide and Specifications 2 ni.com

Front Panel and Connector Pinouts

Front Panel

Table 1 shows the front panel connector and signal descriptions for the NI 5761. Refer to the

Specifications section of this document for additional signal information.

Caution To avoid permanent damage to the NI 5761, disconnect all signals connected to the NI 5761

before powering down the module, and only connect signals after the adapter module has been

powered on by the NI FlexRIO FPGA module.

Table 1. NI 5761 Front Panel Connectors

Device Front Panel Connector Signal Description

AUX I/O Refer to Table 2 for the signal names and descriptions.

D<0..3> LEDs for custom configuration.

CLK IN Provides the NI 5761 with an external Sample clock or

Reference clock.

TRIG Trigger input channel.

CH 0 Analog input channels <0..3>.

CH 1

CH 2

CH 3

NI 5761NI 5761

250 MS/s

Analog Input

D0 D1

D2 D3

CLK IN TRIG CH 0 CH 1 CH 2 CH 3

AUX I/O

©National Instruments Corporation 3 NI 5761R User Guide and Specifications

AUX I/O Connector

Table 2 shows the pins assignments for the AUX I/O connector on the NI 5761.

Caution Connections that exceed any of the maximum ratings of any connector on the NI 5761R

can damage the device and the chassis. NI is not liable for any damage resulting from such signal

connections. For the maximum input and output ratings for each signal, refer to the Specifications

section of this document.

Table 2. NI 5761 AUX I/O Connector Pin Assignments

Micro-D Connector Pin Signal Signal Description

1 AUXIO0 General-purpose digital input or output channels.

2 AUXIO1

3 AUXIO2

4 AUXIO3

5 AUXIO4

6 AUXIO5

7 AUXIO6

8 AUXIO7

9 GND Ground.

10 GND

11 GND

12 GND

13 GND

14 GND

15 GND

NI 5761R User Guide and Specifications 4 ni.com

Block Diagram

Figure 2 shows the NI 5761 block diagram and signal flow to and from the NI 5761 component-level intellectual

property (CLIP) by way of the adapter module and the corresponding NI 5761 CLIP in LabVIEW FPGA.

Figure 2. NI 5761 Connector Signals and NI 5761 CLIP Signal Block Diagram

PFI Input

LabVIEW FPGA CLIPNI 5761 Adapter Module

PFI Output

PFI Write Enable

PFI Connector

Enable

LED <0..3>

Trigger Input

SPI Read

SPI Write

SPI Address

SPI Write Data

SPI Read Data

SPI Device Select

Initialization Done

Reinitialize

Configuration Error

Sample Clock Select

Sample Clock Commit

SPI Idle

Analog FE

IO Module Clock 0

(n = 1, Single Sample CLIP

n = 2, Multiple Sample CLIP)

Multiple

Sample CLIP

Single

Sample CLIP

AI 0

AI 1

AI 2

AI 3

AI 0 Data N

AI 1 Data N

AI 2 Data N

AI 3 Data N

AI 0 Data N–1

AI 1 Data N–1

AI 2 Data N–1

AI 3 Data N–1

Data

Clock

Data

Sample Clock

Clock

Buffer

Internal

Reference

Clock

Synthesizer

Switch

Buffer

Switch

CLK IN

D<0..3>

(LEDs)

AUX I/O

TRIG

CH 0

CH 1

CH 2

CH 3

Switch

Clock

ADC

Interface

IOModSyncClock

1/n

Switches

ADS62P49

Analog

Front End

FET

Buffer

FET

Buffer

Analog

Front End

Analog

Front End

Analog

Front End

AD9512

SPI Engine

Interfacing

with:

Synthesizer Locked

©National Instruments Corporation 5 NI 5761R User Guide and Specifications

NI 5761 Component-Level Intellectual Property (CLIP)

The LabVIEW FPGA Module includes a feature for HDL IP integration called CLIP. NI FlexRIO

devices support two types of CLIP: user-defined and socketed.

•User-defined CLIP allows users to insert HDL IP into an FPGA target, enabling VHDL code to

communicate directly with an FPGA VI.

•Socketed CLIP provides the same IP integration functionality of the user-defined CLIP, but also

allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter module

socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external

adapter module connector interface.

Figure 3 shows the relationship between an FPGA VI and CLIP.

Figure 3. CLIP Relationship

Adapter Module

CLIP Socket

LabVIEW

FPGA VI

User-Defined

CLIP

NI FlexRIO FPGA Module

FPGA

External

I/O Connector

Adapter

Module

Socketed

CLIP

User-Defined

CLIP Fixed I/O

DRAM 0

CLIP Socket

Socketed

CLIP

DRAM 1

CLIP Socket

Socketed

CLIP

Fixed I/O

DRAM0 DRAM1

NI 5761R User Guide and Specifications 6 ni.com

The NI 5761 ships with socketed CLIP items that are used to add module I/O to the LabVIEW project.

The NI 5761 ships with the following CLIP items:

•NI 5761 Multiple Sample CLIP—Generates two samples per clock cycle at a clock rate that is

half the sample rate. The default sample rate is 250 MHz, which sets the default clock rate for this

CLIP at 125 MHz. You can set a lower sample rate by using an external Sample clock. This CLIP

provides access to four analog input channels, eight PFI lines, and an input clock selector that can

be configured to use one of the following settings:

– Internal Sample clock

– Internal Sample clock locked to an external Reference clock through the CLK IN connector

– External Sample clock through the CLK IN connector

– Internal Sample clock locked to an external Reference clock through IoModSyncClock

– External Sample clock through IoModSyncClock

This CLIP also contains an engine to program the CLK chip and ADCs, either through predetermined

settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced

setup. The NI 5761 Multiple Sample CLIP is the default CLIP.

•NI 5761 Single Sample CLIP—Generates one sample per clock cycle at a default sample rate of

250 MHz. You can set a lower sample rate by using an external Sample clock. This CLIP provides

access to four analog input channels, eight PFI lines, and an input clock selector that can be

configured to use one of the following settings:

– Internal Sample clock

– Internal Sample clock locked to an external Reference clock through the CLK IN connector

– External Sample clock through the CLK IN connector

– Internal Sample clock locked to an external Reference clock through IoModSyncClock

– External Sample clock through IoModSyncClock

This CLIP also contains an engine to program the CLK chip and ADCs, either through predetermined

settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced

setup.

Refer to the NI FlexRIO Help in the LabVIEW Help for more information about NI FlexRIO CLIP items,

configuring the NI 5761 with a socketed CLIP, and a list of available socketed CLIP and provided

signals.

Cables

Use the NI CMD-to-CMD cable (NI part number 763194-01) or the NI CMD Single-ended to Pigtail

cable (NI part number 763191-01) to connect signals to your AUX I/O connector. Use any 50 ΩSMA

cable to connect signals to the other connectors on the front panel of your NI 5761. For more information

about connecting I/O signals on your device, refer to the Specifications section of this document.

©National Instruments Corporation 7 NI 5761R User Guide and Specifications

Clocking

The NI 5761 clocks control the sample rate and other timing functions on the device. Table 3 contains

information about the possible NI 5761 clock resources.

Using Your NI 5761R with a LabVIEW FPGA Example VI

The NI FlexRIO Adapter Module Support software includes a variety of example projects to help get

you started creating your LabVIEW FPGA program. This section explains how to use an existing

LabVIEW FPGA example project to generate and acquire samples with the NI 5761R. This example

requires at least one SMA cable for connecting signals to your NI 5761R.

Note Examples available for your device are dependent on the device-specific minimum software

requirements. For more information about software requirements for your device, visit ni.com/

info and enter rdsoftwareversion as the Info Code to determine which minimum software

versions you need for your device.

Each NI 5761R example project includes the following components:

• A LabVIEW FPGA VI that can be compiled and run embedded in FPGA hardware

• A VI that runs in LabVIEW for Windows and interacts with the LabVIEW FPGA VI

Note In NI application software, NI FlexRIO adapter modules are referred to as IO Modules.

Complete the following steps to run an example that acquires a waveform on CH 0 of the NI 5761.

1. Connect one end of an SMA cable to CH 0 on the front panel of the NI 5761 and the other end of

the cable to your device under test (DUT).

2. Launch LabVIEW.

3. In the Getting Started window, click Find Examples to display the NI Example Finder.

4. In the NI Example Finder window, select Hardware Input and Output»FlexRIO»IO Modules»

NI 5761.

5. Select NI 5761 - Getting Started.lvproj.

6. In the Project Explorer window, open NI 5761 - Getting Started (Host).vi under My Computer.

The host VI opens. This VI uses the NI 7952R as the FPGA target by default. If you are using an

NI FlexRIO FPGA module other than the NI 7952R, complete the following steps to change to an

FPGA VI that supports your target.

a. Select Window»Show Block Diagram to open the VI block diagram.

b. On the block diagram, right-click the Open FPGA VI Reference (PXI-7952R) function and

select Configure Open FPGA VI Reference.

Table 3. NI 5761 Clock Sources

Clock Frequency Source Options

Sample Clock 175 MHz to 250 MHz • Internal VCO locked to a Reference clock

• External through the CLK IN connector

• External through IoModSyncClock

Reference Clock 10 MHz • Internal

• External through the CLK IN connector

• External through IoModSyncClock

NI 5761R User Guide and Specifications 8 ni.com

c. In the Configure Open FPGA VI Reference dialog box, click the Browse Project button in

the Open VI section.

d. In the Select VI dialog box that opens, expand the tree view for your device, select the VI

under your device and click OK.

e. Click OK in the Configure Open FPGA VI Reference dialog box.

f. Save the VI.

7. On the front panel, in the RIO Resource box, select an NI 5761R resource that corresponds with

the target configured in step 6.

8. Select AI 0 in the AI Channel box.

9. Set the Trigger Level (V) and the Record Size controls to the desired value.

10. In the Trigger Type box, you can select either Software Trigger or Data Edge. If you select

Software Trigger, the VI acquires data every time you click the Software Trigger button on the

front panel of the VI. If you select Data Edge, the VI acquires data every time an edge occurs.

11. Click the Run button to run the VI.

12. Click the Software Trigger button if you selected Software Trigger in the Trigger Type box. The

VI acquires data and displays the captured waveform on the Acquired Waveform graph as shown

in Figure 4.

13. Click STOP to stop the VI.

14. Close the VI.

Figure 4. NI 5761 - Getting Started (Host) VI Front Panel

©National Instruments Corporation 9 NI 5761R User Guide and Specifications

Creating a LabVIEW Project and Run a VI on an FPGA Target

This section explains how to setup your target and create an FPGA VI and host VI for data

communication. For more detailed information about acquiring data on your NI 5761R, refer to the

example VIs available on your NI FlexRIO Adapter Module Support software.

Creating a Project

1. Launch LabVIEW, or if LabVIEW is already running, select File»New.

2. In the New dialog box, select Project»Empty Project. Click OK. The new project opens in the

Project Explorer window.

3. Save the project as 5761SampleAcq.lvproj.

Creating an FPGA Target VI

1. In the Project Explorer window, right-click My Computer and select New»Targets and

Devices.

2. In the Add Targets and Devices on My Computer dialog box, select the Existing Target or

Device option button and expand the FPGA Target. The target is displayed.

3. Select your device and click OK. The target and target properties are loaded into the project tree.

4. In the Project Explorer window, expand FPGA Target (RIOx, PXI-79xxR).

5. Right-click the FPGA target and select New»FPGA Base Clock.

6. In the Resource pull-down menu, select IO Module Clock 0.

7. Enter 125 MHz in the Compile for single frequency control. Click OK.

8. Right-click the FPGA target and select New»FPGA Base Clock again.

9. In the Resource pull-down menu, select 200 MHz Clock. Click OK.

10. Right-click IO Module and select Properties. In the General category, you can see the available

CLIP for the NI 5761 in the Component Level IP pane. If the category information is dimmed,

select the Enable IO Module checkbox.

11. Select NI 5761 Multi Sample CLIP.

12. In the Clock Selections category, select 200 MHz Clock from the pull-down menu for Clk200.

Leave Clk40 configured as the Top-Leve l Clock. This step is necessary to compile the FPGA

Target VI correctly. Click OK.

Note Configuring these clocks is required for proper CLIP operation. Refer to the NI 5761 CLIP

topics in the NI FlexRIO Help for more information about configuring your clocks.

13. In the Project Explorer window, right-click the FPGA target and select New»VI. A blank VI

opens.

14. Select Window»Show Block Diagram to open the VI block diagram.

15. In the Project Explorer window, expand the IO Module (NI 5761 : NI 5761) tree view.

16. Select AI 0 Data N and AI 0 Data N-1 and drag them onto the block diagram.

17. Add a Timed Loop around the two nodes.

18. Wire an indicator to the output terminals of the IO Module\AI 0 Data N and IO Module\AI 0

Data N-1 nodes.

19. Wire an FPGA Clock Constant to the input node of the Timed Loop. Set this constant to

IO Module Clock 0.

NI 5761R User Guide and Specifications 10 ni.com

Your block diagram should now resemble the block diagram in Figure 5.

Figure 5. 5761SampleAcq (FPGA).vi Block Diagram

Tip Click the Clean Up Diagram button on the toolbar to cleanly organize the VI block diagrams.

20. Save the VI as 5761SampleAcq (FPGA).vi.

21. Close the VI.

22. In the Project Explorer window under My Computer, expand the tree view for your device,

right-click 5761SampleAcq (FPGA).vi and select Compile to compile the files for your target.

The Generating Intermediate Files window opens and displays the compilation progress.

The LabVIEW FPGA Compile Server window opens and runs. The compilation takes several

minutes.

23. When the compilation completes, click the Stop Server button.

24. Click Close in the Successful Compile Report window.

25. Save and close the VI.

26. Save the project.

Creating a Host VI

1. In the Project Explorer window, right-click My Computer and select New»VI. A blank VI opens.

Select Window»Show Block Diagram to open the VI block diagram.

2. Add the Open FPGA VI Reference function, located on the FPGA Interface palette, to the block

diagram.

3. Right-click the Open FPGA VI Reference function, labeled No Target, and select Configure

Open FPGA VI Reference.

4. In the Configure Open FPGA VI Reference dialog box, select the VI option button.

5. In the Select VI window that opens, select 5761SampleAcq (FPGA).vi under your device, and

click OK.

6. Click OK in the Configure Open FPGA VI Reference dialog box. The new target name appears

under the Open FPGA VI Reference function in the block diagram.

7. Add a While Loop to the block diagram.

8. Right-click the stop condition inside the While Loop and select Create Control to create a

STOP control on the VI front panel.

9. Add the Read/Write Control function, located on the FPGA Interface palette, inside the

While Loop.

10. Wire the FPGA VI Reference Out indicator of the Open FPGA VI Reference function to the

FPGA VI Reference In control on the Read/Write Control function.

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