NXP Semiconductors MSC8113 Manuale utente

MSC8113 Reference Manual

Tri Core 16-Bit Digital Signal Processor

MSC8113RM

Rev 0, May 2008

Information in this document is provided solely to enable system and software

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MSC8113RM

Rev. 0

5/2008

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MSC8113 Overview

SC140 Core Overview

System Interface Unit (SIU)

Clocks

Memory Controller

System Bus

Direct Slave Interface (DSI)

Interrupt Processing

Debugging

Programming Reference

MSC8113 Dictionary

Index

Universal Asynchronous Receiver/Transmitter (UART)

External Signals

Reset

Boot Program

Memory Map

Extended Core

Hardware Semaphores

Direct Memory Access (DMA) Controller

Internal Peripheral Bus (IPBus)

Time-Division Multiplexing (TDM) Interface

Timers

General-Purpose Input/Output (GPIO)

MQBus and M2 Memory 10

SQBus 11

I2C Software Module 24

Ethernet Controller 25

MSC8113 Boot Code

1MSC8113 Overview

2SC140 Core Overview

4System Interface Unit (SIU)

7Clocks

12 Memory Controller

13 System Bus

14 Direct Slave Interface (DSI)

17 Interrupt Processing

18 Debugging

AProgramming Reference

BMSC8113 Dictionary

IIndex

Universal Asynchronous Receiver/Transmitter (UART)

External Signals

Reset

Boot Program

Memory Map

Extended Core

Hardware Semaphores

Direct Memory Access (DMA) Controller

Internal Peripheral Bus (IPBus)

Time-Division Multiplexing (TDM) Interface

Timers

General-Purpose Input/Output (GPIO)

MQBus and M2 Memory

SQBus

I2C Software Module

Ethernet Controller

CMSC8113 Boot Code

MSC8113 Reference Manual, Rev. 0

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Contents

About This Book

Before Using This Manual—Important Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii

Audience and Helpful Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii

Notational Conventions and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

Conventions for Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv

Other MSC8113 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii

Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii

1MSC8113 Overview

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.2.1 Extended Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.2.1.1 SC140 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.2.1.2 M1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.1.3 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.1.4 QBus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

1.2.2 Power Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.2.2.1 Extended Core Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.2.2.2 Extended Core Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.2.3 M2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.2.4 System Interface Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.2.4.1 60x-Compatible System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.2.4.2 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.2.5 Direct Slave Interface (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.2.6 Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

1.2.7 Internal and External Bus Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

1.2.8 TDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.2.9 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

1.2.10 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . 1-23

1.2.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

1.2.12 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

1.2.13 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

1.2.14 Interrupt Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

1.2.15 Signal Multiplexing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

1.3 Internal Communication and Semaphores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

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1.3.1 Internal Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

1.3.2 Atomic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

1.3.3 Hardware Semaphores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

2SC140 Core Overview

2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.1 Data Arithmetic Logic Unit (Data ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.1.1.1 Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.1.2 Multiply-Accumulate (MAC) Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.1.3 Bit-Field Unit (BFU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.1.2 Address Generation Unit (AGU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.1.2.1 Stack Pointer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.1.2.2 Bit Mask Unit (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.1.3 Program Sequencer Unit (PSEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.1.4 Enhanced On-Chip Emulation (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.1 AGU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.2 Data Arithmetic Logic Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.2.3 Program Control Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.3 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.4 Additional Programming Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

3External Signals

3.1 Power Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.3 Reset and Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4 Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals . . . . . . . . . 3-4

3.5 Memory Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.6 GPIO, TDM, UART, and Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.7 Dedicated Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

3.8 EOnCE Event and JTAG Test Access Port Signals. . . . . . . . . . . . . . . . . . . . . . 3-27

3.9 Reserved Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

4System Interface Unit (SIU)

4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.1.1 Bus Monitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.1.2 Timers Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.1.3 Time Counter (TMCNT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.1.4 Periodic Interrupt Timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.1.5 SIU and General Software Watchdog Timers. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.1.6 SIU Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

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4.2 SIU Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.2.1 System Configuration and Protection Registers . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.2.2 Periodic Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

5Reset

5.1 Power-On Reset (PORESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.1 Reset Configuration Through the DSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.2 Reset Configuration Through the System Bus . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.3 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.4 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.5 Reset Configuration Writes Through the System Bus. . . . . . . . . . . . . . . . . . . . . 5-9

5.5.1 Single MSC8113 System Configuration From EPROM. . . . . . . . . . . . . . . . . . 5-9

5.5.2 Single Slave MSC8113 Configuration by System Bus Host . . . . . . . . . . . . . 5-10

5.5.3 Multi-MSC8113 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.5.4 Multiple MSC8113 Devices in a System With No EPROM . . . . . . . . . . . . . 5-13

5.6 Reset Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.6.1 Hard Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.6.2 Reset Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

6Boot Program

6.1 Boot Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2 Booting From an External Memory Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.3 Booting from an External Host (DSI or System Bus) . . . . . . . . . . . . . . . . . . . . . 6-4

6.4 Booting From the TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.4.1 Initializing the TDM Physical Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.4.1.1 Receiver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.4.1.2 Transmitter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.4.2 TDM Logical Layer Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.4.2.1 Messages Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.4.2.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.5 Booting From a UART Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.6 Booting from I²C Slave Memory Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.6.1 Procedure Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.6.2 I2C System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

7Clocks

7.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2 Board-Level Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2.1 Single Master Mode Board-Level Clock Distribution . . . . . . . . . . . . . . . . . . . 7-3

7.2.2 Multi-Master Mode Board-Level Clock Distribution. . . . . . . . . . . . . . . . . . . . 7-5

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7.3 Clock Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.4 Clocks Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

8Memory Map

8.1 SC140 Core Internal Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.2 QBus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.3 MQBus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.4 SQBus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.5 IPBus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.6 Local Bus Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

8.7 System Bus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-55

8.8 DSI Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-61

8.9 Pseudo Command Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-79

8.10 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-79

9Extended Core

9.1 SC140 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2 Extended Core Memory (M1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2.1 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.2.1.1 Memory Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.2.1.2 Memory Contention and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.2 Errors and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.2.1 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.2.2 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.3 Extended QBus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.3.1 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.1.1 Fetch Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.2 QBus Execution Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.3.3 QBus Banks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.3.4 Bank Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

9.3.5 Bank Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

9.3.6 Reservation Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.3.7 Setting a Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

9.3.8 Instruction Cacheable Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

9.3.9 EQBS Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18

9.4 Instruction Cache (ICache) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24

9.4.1 ICache Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28

9.4.2 Debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29

9.4.3 Multi-Task Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32

9.4.4 ICache Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33

9.4.4.1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34

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Contents

9.4.4.2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34

9.4.4.3 Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35

9.4.4.4 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35

9.4.4.5 ICache Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36

9.5 Programmable Interrupt Controller (PIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38

9.6 Local Interrupt Controller (LIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38

9.7 Extended Core Power Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39

9.7.1 Extended Core Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39

9.7.2 Extended Core Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39

10 MQBus and M2 Memory

10.1 MQBus Arbitration Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2 M2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.3 Reservation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

11 SQBus

11.1 System Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2 Reservation (Atomic) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2.1 Reservation Operation in the SQBus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2.2 Reservation Operation on the System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2.3 Conditions for Failure of the Reservation Operation . . . . . . . . . . . . . . . . . . . 11-3

12 Memory Controller

12.1 Basic Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.1.1 Address and Address Space Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.1.2 Page Hit Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.1.3 Parity Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.1.4 Transfer Error Acknowledge (TEA) Generation . . . . . . . . . . . . . . . . . . . . . . 12-9

12.1.5 Machine Check Interrupt (MCP) Generation . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

12.1.6 Data Buffer Controls (BCTL[0–1]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

12.1.7 Atomic Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.1.8 Partial Data Valid Indication (PSDVAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.1.9 ECC/Parity Byte-Select (PPBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

12.1.10 Data Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

12.1.11 60x-Compatible Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.1.12 External Memory Controller Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.1.13 External Address Latch Enable Signal (ALE) . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.1.14 BADDR[27–31] Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.2 SDRAM Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

12.2.1 Supported SDRAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14

12.2.2 SDRAM Power-On Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14

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x Freescale Semiconductor

Contents

12.2.3 JEDEC-Standard SDRAM Interface Commands . . . . . . . . . . . . . . . . . . . . . 12-16

12.2.4 Page-Mode Support and Pipeline Accesses . . . . . . . . . . . . . . . . . . . . . . . . . 12-16

12.2.5 Bank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17

12.2.6 BNKSEL Signals in Single-MSC8113 Bus Mode . . . . . . . . . . . . . . . . . . . . 12-18

12.2.7 SDRAM Address Multiplexing (SDAM and BSMA) . . . . . . . . . . . . . . . . . 12-18

12.2.8 SDRAM Read/Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20

12.2.9 SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20

12.2.10 SDRAM Signals: Device-Specific Parameters . . . . . . . . . . . . . . . . . . . . . . . 12-20

12.2.11 SDRAM Signals: General Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . 12-25

12.2.12 SDRAM Signals: mode-set Command Timing. . . . . . . . . . . . . . . . . . . . . . . 12-28

12.2.13 SDRAM Signals: Refresh Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28

12.2.14 SDRAM Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29

12.2.14.1 SDRAM Configuration Example (Page-Based Interleaving) . . . . . . . . . . 12-29

12.2.14.2 SDRAM Configuration Example (Bank-Based Interleaving) . . . . . . . . . . 12-31

12.3 General-Purpose Chip-Select Machine (GPCM). . . . . . . . . . . . . . . . . . . . . . . 12-33

12.3.1 GPCM Signals: Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34

12.3.1.1 Chip-Select Assertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34

12.3.1.2 Chip-Select and Write Enable Deassertion Timing . . . . . . . . . . . . . . . . . . 12-36

12.3.1.3 Relaxed Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37

12.3.1.4 Output Enable (POE) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38

12.3.1.5 Programmable Wait State Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38

12.3.1.6 Extended Hold Time on Read Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40

12.3.2 GPCM Signals: External Access Termination . . . . . . . . . . . . . . . . . . . . . . . 12-42

12.3.3 Boot Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44

12.3.4 Differences Between MPC8xx GPCM and MSC8113 GPCM. . . . . . . . . . . 12-44

12.4 User-Programmable Machines (UPMs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45

12.4.1 Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46

12.4.1.1 Memory Access Requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47

12.4.1.2 UPM Refresh Timer Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48

12.4.1.3 Software Requests—run Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48

12.4.1.4 Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48

12.4.2 Programming the UPMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49

12.4.3 Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49

12.4.4 RAM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50

12.4.4.1 RAM Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51

12.4.4.2 Last Word (LAST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59

12.4.4.3 Address Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59

12.4.4.4 Data Valid and Data Sample Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59

12.4.4.5 Disable Timer Mechanism (TODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60

12.4.4.6 Signal Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60

12.4.4.7 Wait Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60

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