Qorvo PAC25140 Manuale utente

Power Application Controller Battery Management

PRODUCT USER GUIDE

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PAC25140 User Guide Preview

PAC Battery Management System

Multi-Mode Power ManagerTM

Configurable Analog Front EndTM

Application Specific Power DriversTM

Arm®Cortex®-M4F Controller Core

 
PAC25140 Users Guide Preview 
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www.qorvo.com 
Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 
2 of 77 
TABLE OF CONTENTS 
 
1OVERVIEW ........................................................................................................................ 8 
2STYLE AND FORMATTING CONVENTIONS..................................................................... 9 
2.1 Number Representation............................................................................................... 9 
2.2 Formatting Styles......................................................................................................... 9 
3ARCHITECTURAL BLOCK DIAGRAM ..............................................................................10 
4ANALOG REGISTER ACCESS .........................................................................................11 
4.1 Overview.....................................................................................................................11 
4.2 Functional Description ................................................................................................11 
4.3 USART Configuration .................................................................................................12 
4.4 Protocol ......................................................................................................................12 
4.5 Write Register Example ..............................................................................................12 
4.6Read Register Example ..............................................................................................14 
5PAC25140 IO.....................................................................................................................15 
5.1 Overview.....................................................................................................................15 
5.2 ADC Channels ............................................................................................................16 
5.3 Digital Peripheral Pins.................................................................................................17 
6CONFIGURABLE POWER MANAGER .............................................................................19 
6.1 Features .....................................................................................................................19 
6.2 System Block Diagram................................................................................................19 
6.3 Functional Description ................................................................................................19 
6.4 Register Summary ......................................................................................................23 
6.5 Register Detail ............................................................................................................24 
6.5.1 SOC.FAULT.........................................................................................................24 
6.5.2 SOC.STATUS......................................................................................................24 
6.5.3 SOC.MISC...........................................................................................................26 
6.5.4 SOC.PWRCTL.....................................................................................................27 
6.5.5 SOC.FAULTENABLE...........................................................................................28 
6.5.6 SOC.WATCHDOG...............................................................................................29 
6.5.7 SOC.SYSCONF...................................................................................................30 
7CONFIGURABLE ANALOG FRONT-END .........................................................................31 
7.1 Overview.....................................................................................................................31 
7.2 Features .....................................................................................................................31 
7.3 System Block Diagram................................................................................................32 

 
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4 Functional Description ................................................................................................33 
4.1 Register Protection ..............................................................................................33 
4.2 Current Sensing...................................................................................................33 
4.3 IADC 16-bit Sigma-Delta ADC .............................................................................33 
4.4 Over-Current Protection.......................................................................................34 
4.5 Short- Circuit Protection.......................................................................................34 
4.6 Over-Current Charge Protection ..........................................................................34 
4.7 Over-Current Discharge Protection ......................................................................35 
4.8 Battery Over-Voltage Protection...........................................................................35 
4.9 Voltage Sensing...................................................................................................36 
4.10 Measuring Independent Cell Voltages .................................................................36 
4.11 AFE MUX.............................................................................................................37 
4.12 Enabling the CAFE ..............................................................................................37 
4.13 Push-Button (PB) Input ........................................................................................37 
5 Analog I/O 0 (AIO0) ....................................................................................................39 
5.1 AIO0 Block Diagram ............................................................................................39 
Miscellaneous ..................................................................................................................40 
1 General-Purpose Register ..........................................................................................40 
2 AFE Registers.............................................................................................................41 
3 Driver Manager ...........................................................................................................65 
3.1 Block Diagram .....................................................................................................65 
4 Cell Balancing.............................................................................................................65 
4.1 Block Diagram .....................................................................................................66 
5 AFE MUX and EMUX..................................................................................................68 
5.1 AFE MUX.............................................................................................................68 
5.2 EMUX ..................................................................................................................69 
9ARM®CORTEX M4F REFERENCE ..................................................................................72 
1 PAC25xxx Architecture ...............................................................................................73 
2 SYSTEM AND CLOCK CONTROL (SCC) ..................................................................74 
2.1 Overview..............................................................................................................74 
2.2 Features ..............................................................................................................74 
3 MCU MEMORY MAP..................................................................................................76 
LEGAL INFORMATION .....................................................................................................77 
 

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LIST OF FIGURES

Figure 3-1 PAC25140 Architectural Block Diagram...................................................................10

Figure 4-1 PAC25140 Register Access.....................................................................................11

Figure 4-2 Analog Peripheral Register Write Timing .................................................................12

Figure 4-3 Analog Peripheral Register Read Timing .................................................................14

Figure 5-1 GPIO and DPM Block Diagram ................................................................................15

Figure 6-1 Power Manager System Block Diagram...................................................................19

Figure 7-1 Configurable Analog Front End System Block Diagram ...........................................32

Figure 7-2 Push Button Block Diagram .....................................................................................38

Figure 7-3 AIO0 Block Diagram ................................................................................................39

Figure 9-1 EMUX Timing Diagram ............................................................................................71

Figure 9-1 Top Level Block Diagram.........................................................................................73

Figure 9-2 Clock Control Block Diagram ...................................................................................75

Figure 9-3 High Level Memory ..................................................................................................76

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LIST OF TABLES

Table 5-1 PAC25140 ADC Input Pins .......................................................................................16

Table 5-2 PAC25140 Digital Peripheral Pins.............................................................................17

Table 6-1 CPM Register Summary............................................................................................23

Table 8-1 Analog Front End Register Map ................................................................................41

Table 8-2 ADC MUX channels ..................................................................................................68

Table 8-3 AFE MUX channels...................................................................................................69

 
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LIST OF REGISTERS 
Register 6-1 SOC.FAULT (Fault Condition, 00h).......................................................................24 
Register 6-2 SOC.STATUS (System Status, 01h).....................................................................24 
Register 6-3 SOC.MISC (SOC Miscellaneous Configuration, 02h)............................................26 
Register 6-4 SOC.PWRCTL (Power Control, 03h) ....................................................................27 
Register 6-5 SOC.FAULTENABLE (Fault enable, 04h) .............................................................28 
Register 6-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05h) ......................................29 
Register 6-7 SOC.SYSCONF (System Configuration, 2Bh) ......................................................30 
Register 8-1. SOC.AFECTL1 (AFE Control 1, SOC 0x00).......................................................43 
Register 8-2. SOC.AFECTL2 (AFE Control 2, SOC 0x01).......................................................43 
Register 8-3. SOC.DRVCTL (Driver Control, SOC 0x02)........................................................44 
Register 8-4. SOC.AFEMUXCTL (AFE Mux Control, SOC 0x03)............................................44 
Register 8-5. SOC.AFEMUXSEL (AFE Mux Select, SOC 0x04)..............................................44 
Register 8-6. SOC.HIBCTL (Hibernate Control, SOC 0x05) ...................................................46 
Register 8-7. SOC.HIBENTER (Hibernate Enter, SOC 0x06)..................................................47 
Register 8-8. SOC.RSTSTAT (Reset Status, SOC 0x07) ........................................................47 
Register 8-9. SOC.PB (Push Button, SOC 0x08) ....................................................................48 
Register 8-10. SOC.AIO0CFG (Analog I/O 0 Configuration, SOC 0x09)................................49 
Register 8-11. SOC.PROT_KEY (Protection Key, SOC 0x10) ................................................49 
Register 8-12. SOC.SIGMGRCTL1 (Signal Manager Control 1, SOC 0x11) ..........................50 
Register 8-13. SOC.SIGMGRCTL2 (Signal Manager Control 2, SOC 0x12) ..........................50 
Register 8-14. SOC.PROTEN (Reset Status, SOC 0x13)........................................................50 
Register 8-15. SOC.FUSE (Fuse Driver Control, SOC 0x14)..................................................51 
Register 8-16. SOC.PWRFAULTEN (Power Fault Interrupt Enable, SOC 0x15) ...................52 
Register 8-17. SOC.PWRFAULT (Power Fault, SOC 0x16) ....................................................53 
Register 8-18. SOC.TEMPFAULTEN (Temperature Fault Interrupt Enable, SOC 0x17).......53 
Register 8-19. SOC.TEMPFAULT (Temperature Fault Flag, SOC 0x18)................................53 
Register 8-20. SOC.SIGFAULTEN (Signal Manager Fault Interrupt Enable, SOC 0x19)......53 
Register 8-21. SOC.SIGFAULT (Signal Manager Fault Flag, SOC 0x1A) ..............................55 
Register 8-22. SOC.BATRTS (Battery Protection Comparator Real-Time Status, SOC 
0x1B)........................................................................................................................................56 
Register 8-23. SOC.BATOVCFG (Battery Over Voltage Comparator Configuration, SOC 
0x20) ........................................................................................................................................56 
Register 8-24. SOC.BATOVDAC (Battery Over Voltage DAC, SOC 0x21) ............................56 
Register 8-25. SOC.VADCCTL (Voltage ADC Control, SOC 0x22) ........................................57 
Register 8-26. SOC.VADCRESHI (Voltage ADC Result High, SOC 0x23) .............................57 
Register 8-27. SOC.VADCRESLO (Voltage ADC Result Low, SOC 0x24).............................58 
Register 8-28. SOC.IADCCTL (Current ADC Control, SOC 0x25)..........................................58 
Register 8-29. SOC.IADCRESHI (Current ADC Result High, SOC 0x26)...............................58 
Register 8-30. SOC.IADCRESLO (Current ADC Result Low, SOC 0x27) ..............................58 
Register 8-31. SOC.SCPDAC (SCP DAC, SOC 0x28) .............................................................58 
Register 8-32. SOC.SCPCFG (SCP Comparator Configuration, SOC 0x29)........................59 
Register 8-33. SOC.OCDDAC (OCD DAC, SOC 0x2A) ...........................................................59 

 
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Register 8-34. SOC.OCDCFG (OCD Comparator Configuration, SOC 0x2D) ......................60 
Register 8-35. SOC.OCCDAC (OCC DAC, SOC 0x2C) ...........................................................60 
Register 8-36. SOC.OCCCFG (OCC Comparator Configuration, SOC 0x2B) ......................60 
Register 8-37. SOC.CELLEN1 (Cell Enable 1, SOC 0x30)......................................................61 
Register 8-38. SOC.CELLEN2 (Cell Enable 2, SOC 0x31)......................................................61 
Register 8-39. SOC.CELLEN3 (Cell Enable 3, SOC 0x32)......................................................61 
Register 8-40. SOC.CFGCB1 (Configure Cell Balance 1, SOC 0x33)....................................62 
Register 8-41. SOC.CFGCB2 (Configure Cell Balance 2, SOC 0x34)....................................62 
Register 8-42. SOC.CFGCB3 (Configure Cell Balance 3, SOC 0x35)....................................62 
Register 8-43. SOC.GP (General-Purpose Register, SOC 0x40) ...........................................62 
Register 8-44. SOC.CLKOUTCFG (Clock Out Configuration, SOC 0x41) .............................63 
Register 8-45. SOC.WWDTCTL (Windowed Watchdog Timer Control, SOC 0x42) ..............63 
Register 8-46. SOC.WWDTCTR (Windowed Watchdog Timer Counter, SOC 0x43).............64 
Register 8-47. SOC.WWDTCDV (Windowed Watchdog Timer Count Down Value, SOC 
0x44) ........................................................................................................................................64 
Register 8-48. SOC.WWDTWIN (Windowed Watchdog Timer Window, SOC 0x45) .............64 
Register 8-49. SOC.WWDTRST (Windowed Watchdog Timer Reset, SOC 0x46).................64 
Register 8-50. EMUX Packet Structure ...................................................................................70 
 
 

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1 OVERVIEW

This document is the PAC25140 Device User Guide. It details the operation of the analog

peripherals in the PAC25140.

For detailed information on the MCU and Digital Peripherals in the PAC25140, see the

PAC55XX Family User Guide.

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2 STYLE AND FORMATTING CONVENTIONS

This chapter describes the formatting and styles used throughout this document.

2.1 Number Representation

Numbers other than decimal will have a postfix indicator. All numbers use little endian

formatting, with the most significant bit/digit to the left. Digits for binary and hexadecimal

representation are grouped with a single space every four digits to improve readability. Binary

numbers use “b” as a postfix and hexadecimal numbers use “h” as a postfix.

For example, 1011b binary = Bh hexadecimal = 11 decimal.

2.2 Formatting Styles

TYPE

EXAMPLE

DESCRIPTION

RTCCTL

RTCCTL.RTCCLKDIV

separated with a period.

Function selected by

[RTCCTL.RTCCLKDIV]

Within text blocks, functions selected with a register bit setting are

set in brackets. For example [RTCCTL.RTCCLKDIV] means divider

settings /2 to /65536.

Pin Function

PA5

Pin functions use capital letters

Internal signals

PWMA3

Internal signals use italicized font.

Formulas

CLK = FCLK / DIV

Formulas use monospaced text.

Links

Link

Hyperlinks are underlined and blue.

CPU Mnemonic

MRS

CPU Mnemonic uses monospaced text.

Operands

{Rd, }, Rn, Rm

Operands use monospaced italic text.

Code examples

b loopA

Code examples use monospaced text.

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3 ARCHITECTURAL BLOCK DIAGRAM

For Below is an architecture block diagram of the PAC25140 device.

Figure 3-1 PAC25140 Architectural Block Diagram

128kB FLASH

32kB SRAM

CLOCK

CONTROL

RTC/Calendar

GPIO

USART (3)

I2C

CAN

SYSTEM

CONTROL

APB/AHB

PAC25140

Power Application Controller

PX.Y

DEBUG/

ETM

ARM

CORTEX-M4F

CORE

TIMERS (4)

DEAD TIME

(16)

PWM/CC (32)

PWM ENGINE

PX.Y

BRIDGE

WWDT

DTSE

DATA ACQUISITION

AND SEQUENCER

12-BIT

ADC

MUX

1kB INFO

FLASH

GP TIMER (2)

CRC

SOC BUS

POWER

MANAGER

Configurable Analog

Front End (CAFÉ)

PGA ISNSP

ISNSN

HSGD

APPLICATION SPECIFIC

POWER DRIVERS

HSGD

MUX

16-bit

SD ADC

VB1

VB20

PACK+, BAT, VIN

...

Cell

Balance

...

LSGD

LDOs VCORE

VCC33

VSYS

VCCIO

HIGH-

VOLTAGE

BUCK SUPPLY

VIN

DRM

BST

SRC

CSM

Charge Pump VCP

BAT

PACK+

AFE MUX

16-bit

SD ADC

VCP, VP, VSYS

VCC33, VCCIO, VCORE

VREF, VPTAT

FUSE, CHG, DSG

BAT

AIO0

Push

Button

AIO0

CHG

DSG

FUSE

VB20

VB19

...

VB0

VB1

PX.Y

Indice

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