ST STM32F4 Series Manuale utente

March 2015 DocID026304 Rev 3 1/44

AN4488

Application note

Getting started with STM32F4xxxx MCU hardware development

Introduction

This application note is intended for system designers who require an overview of the

hardware implementation of the development board, with focus on features like

•power supply

•package selection

•clock management

•reset control

•boot mode settings

•debug management.

This document shows how to use the high-density high-performance microcontrollers listed

in Table 1, and describes the minimum hardware resources required to develop an

application based on those products.

Detailed reference design schematics are also contained in this document, together with

descriptions of the main components, interfaces and modes.

Table 1. Applicable products

Type Part Number

Microcontrollers

STM32F401xB / STM32F401xC

STM32F401xD / STM32F401xE

STM32F405xx / STM32F407xx

STM32F411xC / STM32F411xE

STM32F415xx / STM32F417xx

STM32F427xx / STM32F429xx

STM32F437xx / STM32F439xx

STM32F446xx

www.st.com

Contents AN4488

2/44 DocID026304 Rev 3

Contents

1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7

2.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . 10

2.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.4 PDR_ON circuitry example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.5 NRST circuitry example (for STM32F411xx and STM32F446xx only) . 14

2.3.6 Regulator OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.7 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 17

3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 Package Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Pinout Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Compatibility within STM32F4x family . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2.2 Compatibility with STM32F1x and STM32F2x families . . . . . . . . . . . . . 23

3.3 Alternate Function mapping to pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 27

4.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.1 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 28

4.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DocID026304 Rev 3 3/44

AN4488 Contents

5.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3 Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.3 Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 33

6.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 34

7 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.3 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

List of tables AN4488

4/44 DocID026304 Rev 3

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Referenced documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 17

Table 4. Package summary (Excluding WCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. WCSP Package summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Pinout summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8. Debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9. SWJ I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 11. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 12. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DocID026304 Rev 3 5/44

AN4488 List of figures

List of figures

Figure 1. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 3. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. PDR_ON simple circuitry example

(not needed for STM32F411xx and STM32F446xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. PDR_ON timings example

(not to scale, not needed for STM32F411xx and STM32F446xx) . . . . . . . . . . . . . . . . . . . 13

Figure 7. NRST circuitry example

(only for STM32F411xx and STM32F446xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. NRST circuitry timings example

(not to scale, only for STM32F411xx and STM32F446xx) . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. BYPASS_REG supervisor reset connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. STM32F4 family compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . 21

Figure 11. STM32F4 family compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . 22

Figure 12. Compatible board design STM32F4xx / STM32F446xx

for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Compatible board design STM32F10xx/STM32F4xx

for LQFP64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx

for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 15. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx

for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16. Compatible board design STM32F2xx and STM32F4xx

for LQFP176 and UFBGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17. STM32CubeMX example screen-shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 18. HSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 19. HSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 20. LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 21. LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 22. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 23. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 24. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 25. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 26. STM32F407IG(H6) microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Reference documents AN4488

6/44 DocID026304 Rev 3

1 Reference documents

The following documents are available on www.st.com.

Table 2. Referenced documents

Reference Title

AN2867 Oscillator design guide for ST microcontrollers

AN2606 STM32 microcontroller system memory boot mode

AN3364 Migration and compatibility guidelines for STM32 microcontroller applications

DocID026304 Rev 3 7/44

AN4488 Power supplies

2 Power supplies

2.1 Introduction

The operating voltage supply (VDD) range is 1.8 V to 3.6 V, which can be reduced down to

1.7 V with some restrictions, as detailed in the product datasheets. An embedded regulator

is used to supply the internal 1.2 V digital power.

The real-time clock (RTC) and backup registers can be powered from the VBAT voltage

when the main VDD supply is powered off.

2.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply that can be

filtered separately, and shielded from noise on the PCB.

•the ADC voltage supply input is available on a separate VDDA pin

•an isolated supply ground connection is provided on the VSSA pin

In all cases, the VSSA pin should be externally connected to same supply ground than

VSS

On packages with 100-pins and above

To ensure a better accuracy on low-voltage inputs, the user can connect a separate external

reference voltage ADC input on VREF+. The voltage on VREF+ may range from (VDDA- 1.2 V)

to VDDA with a minimum of 1.7 V.

When available (depending on package), VREF– must be externally tied to VSSA.

On packages with less than 100-pins

The VREF+ and VREF- pins are not available, they are internally connected to the ADC

voltage supply (VDDA) and ground (VSSA).

2.1.2 Battery backup

To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be

connected to an optional standby voltage supplied by a battery or another source.

The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main

digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power

down reset (PDR) circuitry embedded in the Reset block.

If no external battery is used in the application, it is highly recommended to connect VBAT

externally to VDD.

Power supplies AN4488

8/44 DocID026304 Rev 3

2.1.3 Voltage regulator

The voltage regulator is always enabled after reset. It works in three different modes

depending on the application modes.

•in Run mode, the regulator supplies full power to the 1.2 V domain (core, memories

and digital peripherals)

•in Stop mode, the regulator supplies low power to the 1.2 V domain, preserving the

contents of the registers and SRAM

•in Standby mode, the regulator is powered down. The contents of the registers and

SRAM are lost except for those concerned with the Standby circuitry and the Backup

domain.

Note: Depending on the selected package, there are specific pins that should be connected either

to VSS or VDD to activate or deactivate the voltage regulator. Refer to section “Voltage

regulator “ in datasheet for details.

2.2 Power supply schemes

The circuit is powered by a stabilized power supply, VDD.

Caution: The VDD voltage range is 1.8 V to 3.6 V (down to 1.7 V with some restrictions, see relative

DataSheets for details)

•The VDD pins must be connected to VDD with external decoupling capacitors: one

single Tantalum or Ceramic capacitor (min. 4.7 µF typ.10 µF) for the package + one

100 nF Ceramic capacitor for each VDD pin.

•The VBAT pin can be connected to the external battery (1.65 V < VBAT < 3.6 V). If no

external battery is used, it is recommended to connect this pin to VDD with a 100 nF

external ceramic decoupling capacitor.

•The VDDA pin must be connected to two external decoupling capacitors (100 nF

Ceramic + 1 µF Tantalum or Ceramic).

•The VREF+ pin can be connected to the VDDA external power supply. If a separate,

external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitors must

be connected on this pin. In all cases, VREF+ must be kept between (VDDA-1.2 V) and

VDDA with minimum of 1.7 V.

•must be kept between 1.65 V and VDDA.

•Additional precautions can be taken to filter analog noise:

–V

DDA can be connected to VDD through a ferrite bead.

–TheV

REF+ pin can be connected to VDDA through a resistor (typ. 47 Ω).

•For the voltage regulator configuration, there is specific BYPASS_REG pin (not

available on all packages) that should be connected either to VSS or VDD to activate or

deactivate the voltage regulator specific.

– Refer to Section 2.3.6 and section "Voltage regulator" of the related device

datasheet for details.

•When the voltage regulator is enabled, VCAP1 and VCAP2 pins must be connected to

2*2.2 µF LowESR < 2ΩCeramic capacitor (or 1*4.7 µF LowESR < 1ΩCeramic

capacitor if only VCAP1 pin is provided on some packages).

DocID026304 Rev 3 9/44

AN4488 Power supplies

Figure 1. Power supply scheme

1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and

1 µF) must be connected.

2. VCAP2 is not available on all packages. In that case, a single 4.7 µF (ESR < 1Ω) is connected to VCAP1

3. VREF+ is either connected to VREF+ or to VDDA (depending on package).

4. VREF- is either connected to VREF- or to VSSA (depending on package).

5. N is the number of VDD and VSS inputs.

6. Refer to section “Voltage regulator”in datasheet (Table 1) to connect BYPASS_REG and PDR_ON pins.

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Power supplies AN4488

10/44 DocID026304 Rev 3

2.3 Reset & power supply supervisor

2.3.1 Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from

1.8 V.

The device remains in the Reset mode as long as VDD is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit. For more details concerning the

power on/power down reset threshold, refer to the electrical characteristics in the product

datasheets.

Figure 2. Power-on reset/power-down reset waveform

1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge is

1.70 V (typ.). Refer to STM32F4xxxx datasheets for actual value.

The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through

the PDR_ON pin. An external power supply supervisor should monitor VDD and should

maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON

should be connected to this external power supply supervisor. See Section 2.3.4 and

Section 2.3.5 for details.

2.3.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold

selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate

whether VDD is higher or lower than the PVD threshold. This event is internally connected to

EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD

output interrupt can be generated when VDD drops below the PVD threshold and/or when

VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge

configuration. As an example the service routine can perform emergency shutdown tasks.

6$$

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AIB

60/20$2

FALLINGEDGE

60/20$2

RISINGEDGE

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