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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TRF7963A

SLOS758G –DECEMBER 2011–REVISED MARCH 2020

TRF7963A Fully Integrated 13.56-MHz RFID Reader/Writer IC

For ISO/IEC 14443A, ISO/IEC 14443B, and NFC Standards

1 Device Overview

1.1 Features

• Completely Integrated Protocol Handling for

ISO/IEC 14443 A and B, NFC Forum Device

Types 1 to 4, and FeliCa™

• Input Voltage Range: 2.7 VDC to 5.5 VDC

• Programmable Output Power:

+20 dBm (100 mW) or +23 dBm (200 mW)

• Programmable I/O Voltage Levels:

1.8 VDC to 5.5 VDC

• Programmable System Clock Frequency Output

(RF, RF/2, RF/4)

• Programmable Modulation Depth

• Dual Receiver Architecture With RSSI for

Elimination of "Read Holes" and Adjacent Reader

System or Ambient In-Band Noise Detection

• Programmable Power Modes for Ultra-Low-Power

System Design (Power Down <0.5 µA)

• Parallel or SPI Interface

• Integrated Voltage Regulator for Microcontroller

Supply

• Temperature Range: –25°C to 85°C

• 32-Pin QFN Package (5 mm × 5 mm) (RHB)

1.2 Applications

• Secure Access Control

• Digital Door Locks

• Medical Systems

• Transport Ticketing

• Event Ticketing

1.3 Description

The TRF7963A device is an integrated analog front-end (AFE) and data-framing device for a 13.56-MHz

RFID reader/writer system that supports ISO/IEC 14443 A and B and Sony FeliCa. Built-in programming

options make it suitable for a wide range of applications for proximity identification systems.

The reader is configured by selecting the desired protocol in the control registers. Direct access to all

control registers allows fine tuning of various reader parameters as needed.

The TRF7963A device supports data rates up to 848 kbps with all framing and synchronization tasks for

the ISO protocols onboard. The device also supports reader/writer mode for NFC Forum tag types 1, 2, 3,

and 4. NFC Forum tag types 2, 3, and 4 are supported with the built-in protocol decoders used in Direct

Mode 2. NFC Forum tag type 1 requires the use of Direct Mode 0. Other standards and custom protocols

can also be implemented by using Direct Mode 0. Direct Mode 0 lets the user fully control the AFE and

also gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the

associated (extracted) clock signal.

The receiver system has a dual-input receiver architecture to maximize communication robustness. The

receivers also include various automatic and manual gain control options. The received signal strength

from transponders, ambient sources, or internal levels is available in the RSSI register.

A SPI or parallel interface can be used for the communication between the MCU and the TRF7963A

reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a

12-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed

so the MCU can process the data in real time.

The TRF7963A device supports a wide supply voltage range of 2.7 V to 5.5 V and data communication

levels from 1.8 V to 5.5 V for the MCU I/O interface.

The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm)

equivalent into a 50-Ωload when using a 5-V supply and supports OOK and ASK modulation with

selectable modulation depth.

TRF796xA MCU

(MSP430 or ARM)

Matching

VDD_X VDD_I/O

TX_OUT

RX_IN 1

RX_IN 2

VSS VIN

Parallel

or SPI

Supply

2.7 V to 5.5 V

VDD

Crystal

13.56 MHz

XIN

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The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and

additional external circuits within the reader system.

To evaluate the latest products in the TRF79xx product family – TRF7970A and TRF7964A – see the NFC

Transceiver Booster Pack.

Documentation,Tools, Reference Designs, and Software,Samples

(1) For more information, see Section 9,Mechanical Packaging and Orderable Information.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE

TRF7963ARHB VQFN (32) 5 mm × 5 mm

1.4 Application Block Diagram

Figure 1-1 shows a typical application block diagram.

Figure 1-1. Application Block Diagram

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Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Application Block Diagram ........................... 2

2 Revision History ......................................... 4

3 Device Characteristics.................................. 5

3.1 Related Products ..................................... 5

4 Terminal Configuration and Functions.............. 6

4.1 Pin Diagrams ......................................... 6

4.2 Signal Descriptions................................... 6

5 Specifications ............................................ 8

5.1 Absolute Maximum Ratings .......................... 8

5.2 ESD Ratings.......................................... 8

5.3 Recommended Operating Conditions................ 8

5.4 Electrical Characteristics ............................. 9

5.5 Thermal Resistance Characteristics ................ 10

5.6 Switching Characteristics ........................... 10

6 Detailed Description ................................... 11

6.1 Functional Block Diagram........................... 11

6.2 Power Supplies ..................................... 11

6.3 Supply Arrangements ............................... 12

6.4 Supply Regulator Settings .......................... 13

6.5 Power Modes ....................................... 14

6.6 Receiver – Analog Section.......................... 17

6.7 Receiver – Digital Section........................... 18

6.8 Oscillator Section ................................... 21

6.9 Transmitter - Analog Section........................ 22

6.10 Transmitter - Digital Section ........................ 22

6.11 Transmitter – External Power Amplifier or

Subcarrier Detector ................................. 23

6.12 Communication Interface............................ 23

6.13 Direct Commands from MCU to Reader ............ 39

6.14 Register Description................................. 42

7 Applications, Implementation, and Layout........ 58

7.1 TRF7963A Reader System Using SPI With SS

Mode ................................................ 58

7.2 System Design ...................................... 59

8 Device and Documentation Support ............... 61

8.1 Getting Started and Next Steps..................... 61

8.2 Device Nomenclature ............................... 61

8.3 Tools and Software ................................. 62

8.4 Documentation Support............................. 62

8.5 Support Resources.................................. 62

8.6 Trademarks.......................................... 62

8.7 Electrostatic Discharge Caution..................... 63

8.8 Export Control Notice ............................... 63

8.9 Glossary............................................. 63

9 Mechanical, Packaging, and Orderable

Information .............................................. 64

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from May 18, 2017 to March 11, 2020 Page

• Removed references to obsolete EVMs .......................................................................................... 2

• Corrected typo (changed "...and 3.4 V for VDD_A and VDD_A" to "...and 3.4 V for VDD_A and VDD_X") in

Section 6.3,Supply Arrangements................................................................................................ 13

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3 Device Characteristics

Table 3-1 lists the supported protocols.

Table 3-1. Supported Protocols

DEVICE ISO/IEC 14443 A AND B NFC Forum

TYPES 1 TO 4

106 kbps 212 kbps 424 kbps 848 kbps

TRF7963A ✓✓✓✓✓

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TI Wireless Connectivity Connect more with the industry’s broadest wireless connectivity

portfolio.

Products for NFC / RFID TI provides one of the industry’s most differentiated NFC and RFID product

portfolios and is your solution to meet a broad range of NFC connectivity and RFID

identification needs.

Companion Products for TRF7963A Review products that are frequently purchased or used with this

product.

Reference Designs for TRF7963A The TI Designs Reference Design Library is a robust reference

design library that spans analog, embedded processor, and connectivity. Created by TI

experts to help you jump start your system design, all TI Designs include schematic or block

diagrams, BOMs, and design files to speed your time to market. Search and download

designs at ti.com/tidesigns.

I/O_6

I/O_5

I/O_4

I/O_3

I/O_2

I/O_1

I/O_0

I/O_7

VIN

VDD_RF

VDD_PA

TX_OUT

VSS_PA

VSS_RX

RX_IN1

VDD_A

OSC_IN

OSC_OUT

VSS_D

SYS_CLK

DATA_CLK

EN2

VDD_X

VSS

ASK/OOK

IRQ

MOD

VSS_A

VDD_I/O

RX_IN2

9 10 11 13 1412 15 16

32 31 30 28 2729 26 25

Thermal Pad

(connect to ground)

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SLOS758G –DECEMBER 2011–REVISED MARCH 2020

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(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the 32-pin RHB package.

Figure 4-1. 32-Pin RHB Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1. Signal Descriptions

TERMINAL TYPE (1) DESCRIPTION

NO. NAME

1 VDD_A OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry

2 VIN SUP External supply input to chip (2.7 V to 5.5 V)

3 VDD_RF OUT Internal regulated supply (2.7 V to 5 V); normally connected to VDD_PA (pin 4)

4 VDD_PA INP Supply for PA; normally connected externally to VDD_RF (pin 3)

5 TX_OUT OUT RF output (selectable output power: 100 mW or 200 mW, with VDD = 5 V)

6 VSS_PA SUP Negative supply for PA; normally connected to circuit ground

7 VSS_RX SUP Negative supply for receive inputs; normally connected to circuit ground

8 RX_IN1 INP Main receive input

9 RX_IN2 INP Auxiliary receive input

10 VSS SUP Chip substrate ground

11 BAND_GAP OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference

12 ASK/OOK BID Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 and 1.

It can be configured as an output to provide the received analog signal output.

13 IRQ OUT Interrupt request

14 MOD INP External data modulation input for direct mode 0 or 1

OUT Subcarrier digital data output (see register 0x1A and 0x1B definitions)

15 VSS_A SUP Negative supply for internal analog circuits. Connected to GND.

16 VDD_I/O INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded.

17 I/O_0 BID I/O pin for parallel communication

18 I/O_1 BID I/O pin for parallel communication

19 I/O_2 BID I/O pin for parallel communication

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Table 4-1. Signal Descriptions (continued)

TERMINAL TYPE (1) DESCRIPTION

NO. NAME

20 I/O_3 BID I/O pin for parallel communication

21 I/O_4 BID I/O pin for parallel communication

Slave select signal in SPI mode

22 I/O_5 BID I/O pin for parallel communication

Data clock output in direct mode 1

23 I/O_6 BID

I/O pin for parallel communication

MISO for serial communication (SPI)

Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0

24 I/O_7 BID I/O pin for parallel communication.

MOSI for serial communication (SPI)

25 EN2 INP Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power

down mode 2 (for example, to supply the MCU).

26 DATA_CLK INP Data clock input for MCU communication (parallel and serial)

27 SYS_CLK OUT If EN = 1 (EN2 = don't care) the system clock for the MCU is configured with register 0x09 (off,

3.39 MHz, 6.78 MHz, or 13.56 MHz).

If EN = 0 and EN2 = 1, the system clock is set to 60 kHz.

28 EN INP Chip enable input (if EN = 0, then the chip is in sleep or power-down mode)

29 VSS_D SUP Negative supply for internal digital circuits

30 OSC_OUT OUT Crystal or oscillator output

31 OSC_IN INP Crystal or oscillator input

32 VDD_X OUT Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, an

MCU)

PAD PAD SUP Chip substrate ground

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to substrate ground terminal VSS.

(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability or lifetime of the device.

5 Specifications

5.1 Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted) (2)

MIN MAX UNIT

Input voltage range, VIN –0.3 6 V

Maximum current, IIN 150 mA

Maximum operating virtual junction temperature, TJ(3) Any condition 140 °C

Continuous operation, long-term reliability 125

Storage temperature, TSTG –55 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22‑C101(2) ±500

Machine model (MM) ±200

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VIN Operating input voltage 2.7 5 5.5 V

TAOperating ambient temperature –25 25 85 °C

TJOperating virtual junction temperature –25 25 125 °C

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(1) Antenna driver output resistance

(2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1

(3) Depending on the crystal parameters and components

(4) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output

resistance of 400 Ω(12-ns time constant when 30-pF load is used).

5.4 Electrical Characteristics

TYP operating conditions are TA= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)

MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature

(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IPD1 Supply current in power down mode 1 All building blocks disabled, including supply-

voltage regulators; measured after 500-ms

settling time (EN = 0, EN2 = 0) <0.5 5 µA

IPD2 Supply current in power down mode 2

(sleep mode) The SYS_CLK generator and VDD_X remain

active to support external circuitry, measured

after 100-ms settling time (EN = 0, EN2 = 1) 120 200 µA

ISTBY Supply current in standby mode Oscillator running, supply-voltage regulators in

low-consumption mode (EN = 1, EN2 = x) 1.9 3.5 mA

ION1 Supply current without antenna driver

current Oscillator, regulators, RX, and AGC are active,

TX is off 10.5 14 mA

ION2 Supply current in TX (half power) Oscillator, regulators, RX, AGC, and TX

active, POUT = 100 mW 70 78 mA

ION3 Supply current in TX (full power) Oscillator, regulators, RX, AGC, and TX

active, POUT = 200 mW 130 170 mA

VPOR Power-on reset voltage Input voltage at VIN 1.4 2 2.6 V

VBG Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V

VDD_A Regulated output voltage for analog

circuitry (pin 1) VIN = 5 V 3.1 3.5 3.8 V

VDD_X Regulated supply for external circuitry Output voltage pin 32, VIN = 5 V 3.1 3.4 3.8 V

IVDD_Xmax Maximum output current of VDD_X Output current pin 32, VIN = 5 V 20 mA

RRFOUT Antenna driver output resistance(1) Half-power mode, VIN = 2.7 V to 5.5 V 8 12 Ω

Full-power mode, VIN = 2.7 V to 5.5 V 4 6

RRFIN RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ

VRF_INmax Maximum RF input voltage at RX_IN1

or RX_IN2 VRF_INmax should not exceed VIN 3.5 Vpp

VRF_INmin Minimum RF input voltage at RX_IN1

or RX_IN2 (input sensitivity)(2) fSUBCARRIER = 424 kHz 1.4 2.5 mVpp

fSUBCARRIER = 848 kHz 2.1 3

fSYS_CLK SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 25 60 120 kHz

fCCarrier frequency Defined by external crystal 13.56 MHz

tCRYSTAL Crystal run-in time Time until oscillator stable bit is set (register

0x0F) (3) 5 ms

fD_CLKmax Maximum DATA_CLK frequency(4) Depends on capacitive load on the I/O lines,

recommendation is 2 MHz(4) 2 4 10 MHz

VIL Input voltage, logic low I/O lines, IRQ, SYS_CLK, DATA_CLK, EN,

EN2 0.2 ×

VDD_I/O V

VIH Input voltage threshold, logic high I/O lines, IRQ, SYS_CLK, DATA_CLK, EN,

EN2 0.8 ×

VDD_I/O V

ROUT Output resistance, I/O_0 to I/O_7 500 800 Ω

RSYS_CLK Output resistance RSYS_CLK 200 400 Ω

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(1) This data was taken using the JEDEC standard high-K test PCB.

(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.

Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-

term reliability.

5.5 Thermal Resistance Characteristics

PACKAGE RθJC RθJA(1) POWER RATING(2)

TA≤25°C TA≤85°C

RHB (32) 31°C/W 36.4°C/W 2.7 W 1.1 W

(1) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output

resistance of 400 Ω(12-ns time constant when 30-pF load is used).

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tLO/HI DATA_CLK time, high or low (one half

of DATA_CLK at 50% duty cycle) Depends on capacitive load on the I/O lines (1) 50 62.5 250 ns

tSTE,LEAD Slave select lead time, slave select

low to clock 200 ns

tSTE,LAG Slave select lag time, last clock to

slave select high 200 ns

tSU,SI MOSI input data setup time 15 ns

tHD,SI MOSI input data hold time 15 ns

tSU,SO MISO input data setup time 15 ns

tHD,SO MISO input data hold time 15 ns

tVALID,SO MISO output data valid time DATA_CLK edge to MISO valid, CL= <30 pF 30 50 75 ns

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