Texas Instruments MSP430FG47x Manuale utente

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

DLow Supply-Voltage Range: 1.8 V to 3.6 V

DUltra-Low Power Consumption:

Active Mode: 262 Aat1MHz,2.2V

Standby Mode: 1.1 A

Off Mode (RAM Retention): 0.1 A

DFive Power-Saving Modes

DWake-Up From Standby Mode in

Less Than 6 s

D16-Bit RISC Architecture,

125-ns Instruction Cycle Time

D16-Bit Sigma-Delta Analog-to-Digital (A/D)

Converter With Internal Reference and Five

Differential Analog Inputs

DDual 12-Bit Digital-to-Analog (D/A)

Converter

DDual Configurable Operational Amplifiers

D16-Bit Timer_A With Three

Capture/Compare Registers

D16-Bit Timer_B With Three

Capture/Compare-With-Shadow Registers

DTwo Universal Serial Communication

Interfaces (USCI)

USCI_A0

-- Enhanced UART Supporting

Auto-Baudrate Detection

-- IrDA Encoder and Decoder

-- Synchronous SPI

USCI_B0

-- I 2C

-- Synchronous SPI

DIntegrated LCD Driver With Contrast

Control for Up to 128 Segments

DBrownout Detector

DBasic Timer With Real-Time Clock Feature

DSupply Voltage Supervisor/Monitor With

Programmable Level Detection

DOn-Chip Comparator

DSerial Onboard Programming,

No External Programming Voltage Needed

Programmable Code Protection by Security

Fuse

DBootstrap Loader

DOn-Chip Emulation Module

DMSP430FG47x Family Members Include

MSP430FG477: 32KB+256B Flash Memory

2KB RAM

MSP430FG478: 48KB+256B Flash Memory

2KB RAM

MSP430FG479: 60KB+256B Flash Memory

2KB RAM

DAvailable in 113-Ball BGA (ZQW) and

80-Pin QFP (PN) Packages (see Available

Options)

DFor Complete Module Descriptions, See the

MSP430x4xx Family User’s Guide,

Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code

efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less

than 6 s.

The MSP430FG47x is a microcontroller configuration with two 16-bit timers, a basic timer with a real-time clock,

a high performance 16-bit sigma-delta A/D converter, dual 12-bit D/A converters, two configurable operational

amplifiers, two universal serial communication interface, 48 I/O pins, and a liquid crystal display driver.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote

controls, thermostats, digital timers, hand-held meters, etc.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range

from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage

because very small parametric changes could cause the device not to meet its published specifications. These devices have limited

built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

2POST OFFICE BOX 655303 DALLAS, TEXAS 75265

AVAILABLE OPTIONS†

PACKAGED DEVICES‡

TAPLASTIC 113-BALL BGA (ZQW) PLASTIC 80-PIN QFP (PN)

-- 4 0 Cto85C

MSP430FG477IZQW

MSP430FG478IZQW

MSP430FG479IZQW

MSP430FG477IPN

MSP430FG478IPN

MSP430FG479IPN

†For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

‡Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

DEVELOPMENT TOOL SUPPORT

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging

and programming through easy to use development tools. Recommended hardware options include the

following:

DDebugging and Programming Interface

-- MSP--FET430UIF (USB)

-- MSP--FET430PIF (Parallel Port)

DDebugging and Programming Interface with Target Board

-- MSP--FET430U80 (PN package)

DProduction Programmer

-- MSP--GANG430

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

pin designation, MSP430FG47xIZQW

Note: For terminal assignments, see the MSP430xG47x Terminal Functions table.

A3 A4 A5 A6 A7 A8 A9 A10

E5 E6 E7 E8

A11

B11

C11

D11

E11

F11

G11

H11

J11

K11

L11

M11

A12

B12

C12

D12

E12

F12

G12

H12

J12

K12

L12

M12M3 M4 M5 M6 M7 M8 M9 M10

L3 L4 L5 L6 L7 L8 L9 L10

B3 B4 B5 B6 B7 B8 B9 B10

H5 H6 H7 H8

D4 D5 D6 D7 D8 D9

J4 J5 J6 J7 J8 J9

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

4POST OFFICE BOX 655303 DALLAS, TEXAS 75265

pin designation, MSP430FG47xIPN

80-pin

IPN PACKAGE

(TOP VIEW)

DVCC1 60

80 79

P6.3/A1+/OA1O

P6.4/A1-/OA1FB

P6.5/OA0I2 (SW0B)

P6.6/OA1I1 (SW1A)

P6.7/OA1I2/SVSIN (SW1B)

XIN

XOUT

VREF

GND

P2.6/CAOUT/S2

P2.7/S3

P4.7/S4

P4.6/S5

P4.5/S6

P4.0/S11

S12

S13

S14

S15

S17

S18

S19

P5.0/S20

P5.1/S21

S22

P3.2/UCB0SOMI/UCB0SCL/S27

P3.1/UCB0SIMO/UCB0SDA/S26

P3.0/UCB0STE/UCA0CLK

P5.7/R03

DVCC2

DVSS1

DVSS2

P6.2/OA0I1 (SW0A)

P6.1/A0-/OA0FB

P6.0/A0+/OA0O

RST/NMI

TCK

TMS

TDI/TCLK

TDO/TDI

P5.6/LCDREF/R13

78 77 76 75 74 73 72 71 70 69 68 67 66 65

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

64 63 62 61

S23

38 39 40

P4.4/S7

P4.3/S8

P4.2/S9

P4.1/S10 17

P3.7/S31

P3.6/S30

P3.5/S29

P3.4/S28

P3.3/UCB0CLK/UCA0STE

S24

S25

COM0

P5.2/COM1

P5.3/COM2

P5.4/COM3

P2.5/UCA0RXD/UCA0SOMI

P2.4/UCA0TXD/UCA0SIMO

P2.3/TB2

P2.2/TB1

P2.1/TB0/S0

P2.0/TA2/S1

P1.7/CA1/A2+

P1.6/CA0/A2-/OA0I0/DAC0

P1.5/TACLK/ACLK/A3+

P1.4/TBCLK/SMCLK/A3-/OA1I0/DAC1

P1.3/TBOUTH/SVSOUT/A4+/OA1I3 (SW1C)

P1.2/TA1/A4-/OA0I3 (SW0C)

P1.1/TA0/MCLK/OA1RFB

P1.0/TA0/OA0RFB

AVCC

AVSS

LCDCAP/R33

P5.5/R23

XT2OUT

XT2IN

S16

GND

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

functional block diagram

Oscillators

FLL+

Brownout

Protection

SVS,

SVM

RST/NMI

DVCC1/2 DVSS1/2

MCLK

Watchdog

WDT+

15-Bit

Timer_A3

3 CC

Registers

CPU

64kB

incl. 16

Registers

EEM

JTAG

Interface

OA0, OA1

2 OpAmps

Basic

Timer &

Real-

Time

Clock

LCD_A

128

Segments

1,2,3,4

Mux

Timer_B3

3 CC

Registers,

Shadow

Reg

SD16_A

with

Buffer

1 Channel

Sigma-

Delta A/D

Converter

Comparator

AVCC AVSS P1.x/P2.x

2x8

P3.x/P4.x

P5.x/P6.x

4x8

SMCLK

ACLK

MDB

MAB

DAC12

12-Bit

Channels

Voltage

Out

Ports

P1/P2

2x8 I/O

Interrupt

capability

XIN/

XT2IN

XOUT/

XT2OUT

RAM

2kB

Flash

60kB

48kB

32kB

USCI A0

UART/

LIN,

IrDA, SPI

USCI B0

SPI, I2C

Ports

P3/P4

P5/P6

4x8 I/O

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

6POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NO.

NAME 80

113

AVCC 52 F12 Analog supply voltage, positive terminal.

AVSS 53 E12 Analog supply voltage, negative terminal.

DVCC1 1A1 Digital supply voltage, positive terminal. Supplies all digital parts.

DVSS1 79 A3 Digital supply voltage, negative terminal. Supplies all digital parts.

DVCC2 80 A2 Digital supply voltage, positive terminal. Supplies all digital parts.

DVSS2 78 B2

B3 Digital supply voltage, negative terminal. Supplies all digital parts.

P1.0/TA0/

OA0RFB 58 C11 I/O

General-purpose digital I/O pin

Timer_A, capture: CCI0A input, compare: Out0 output

Range switch to OA0 output

BSL transmit

P1.1/TA0/MCLK/

OA1RFB 57 C12 I/O

General-purpose digital I/O pin

Timer_A, capture: CCI0B input, compare: Out0 output

MCLK signal output

Range switch to OA1 output

BSL receive

P1.2/TA1/A4--/

OA0I3 (SW0C) 56 D11 I/O

General-purpose digital I/O pin

Timer_A, capture: CCI1A input, compare: Out1 output

SD16 negative analog input A4

OA0, analog input I3

P1.3/TBOUTH/

SVSOUT/A4+/

OA1I3 (SW1C)

55 D12 I/O

General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output

switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB2

SVS comparator output

SD16 positive analog input A4

OA1, analog input I3

P1.4/TBCLK/

SMCLK/A3--/

OA1I0/DAC1

54 E11 I/O

General-purpose digital I/O pin/

Timer_B, clock signal TBCLK input

SMCLK signal output

SD16 negative analog input A3

OA1, analog input I0

DAC12.1 output

P1.5/TACLK/

ACLK/A3+ 51 F11 I/O

General-purpose digital I/O pin

Timer_A, clock signal TACLK input

ACLK signal output

SD16 positive analog input A3

P1.6/CA0/A2--/

OA0I0/DAC0 50 G12 I/O

General-purpose digital I/O pin

Comparator_A input 0

SD16 negative analog input A2

OA0, analog input I0

DAC12.0 output

P1.7/CA1/A2+ 49 G11 I/O

General-purpose digital I/O pin

Comparator_A input 1

SD16 positive analog input A2

P2.0/TA2/S1 4C2

C3 I/O

General-purpose digital I/O pin

Timer_A, capture: CCI2A/B input, compare: Out2 output

LCD segment output 1

P2.1/TB0/S0 3C1 I/O

General-purpose digital I/O pin

Timer_B, capture: CCI0A/B input, compare: Out0 output

LCD segment output 0

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NO.

NAME 80

113

P2.2/TB1 2B1 I/O General-purpose digital I/O pin

Timer_B, capture: CCI1A/B input, compare: Out1 output

P2.3/TB2 77 B4 I/O General-purpose digital I/O pin

Timer_B, capture: CCI2A/B input, compare: Out2 output

P2.4/UCA0TXD/

UCA0SIMO 76 A4 I/O General-purpose digital I/O pin

USCIA transmit data output in UART mode, slave data in/master out in SPI mode

P2.5/UCA0RXD/

UCA0SOMI 75 D4 I/O General-purpose digital I/O pin

USCI A0 receive data input in UART mode, slave data out/master in in SPI mode

P2.6/CAOUT/S2 5D1 I/O

General-purpose digital I/O pin

Comparator_A output

LCD segment output 2

P2.7/S3 6D2 I/O General-purpose digital I/O pin

LCD segment output 3

P3.0/UCB0STE/

UCA0CLK 41 M12 I/O General-purpose digital I/O pin

USCI B0 slave transmit enable/USCI A0 clock input/output

P3.1/UCB0SIMO/

UCB0SDA/S26 42 L12 I/O

General-purpose digital I/O pin

USCI B0 slave in/master out in SPI mode, SDA I2CdatainI

2C mode

LCD segment output 26

P3.2/UCB0SOMI/

UCB0SCL/S27 43 K11 I/O

General-purpose digital I/O pin

USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode

LCD segment output 27

P3.3/UCB0CLK/

UCA0STE 44 K12 I/O General-purpose digital I/O

USCI B0 clock input/output, USCI A0 slave transmit enable

P3.4/S28 45 J11 I/O General-purpose digital I/O pin

LCD segment output 28

P3.5/S29 46 J12 I/O General-purpose digital I/O pin

LCD segment output 29

P3.6/S30 47 H11 I/O General-purpose digital I/O pin

LCD segment output 30

P3.7/S31 48 H12 I/O General-purpose digital I/O pin

LCD segment output 31

P4.0/S11 18 K2 I/O General-purpose digital I/O pin

LCD segment output 11

P4.1/S10 17 K1 I/O General-purpose digital I/O pin

LCD segment output 10

P4.2/S9 16 J2 I/O General-purpose digital I/O pin

LCD segment output 9

P4.3/S8 15 J1 I/O General-purpose digital I/O pin

LCD segment output 8

P4.4/S7 14 H2 I/O General-purpose digital I/O pin

LCD segment output 7

P4.5/S6 13 H1 I/O General-purpose digital I/O pin

LCD segment output 6

P4.6/S5 12 G2 I/O General-purpose digital I/O pin

LCD segment output 5

P4.7/S4 11 G1 I/O General-purpose digital I/O pin

LCD segment output 4

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

8POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NO.

NAME 80

113

COM0 33 L8 OCommon output, COM0--3 are used for LCD backplanes

P5.0/S20 27 L5 I/O General-purpose digital I/O pin

LCD segment output 20

P5.1/S21 28 M5 I/O General-purpose digital I/O pin

LCD segment output 21

P5.2/COM1 34 M8 I/O General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

P5.3/COM2 35 L9 I/O General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

P5.4/COM3 36 M9 I/O General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

LCDCAP/R33 37 J9 I/O Capacitor connection for LCD charge pump

input port of most positive analog LCD level (V4)

P5.5/R23 38 M10 I/O General-purpose digital I/O pin

input port of the second most positive analog LCD level (V3)

P5.6/LCDREF/

R13 39 L10 I/O General-purpose digital I/O pin

External LCD reference voltage input

input port of the third most positive analog LCD level (V3 or V2)

P5.7/R03 40 M11 I/O General-purpose digital I/O pin

input port of the fourth most positive analog LCD level (V1)

P6.0/A0+/OA0O 67 B8 I/O

General-purpose digital I/O pin

SD16 positive analog input A0

OA0, output

P6.1/A0--/OA0FB 66 B9 I/O

General-purpose digital I/O pin

SD16 positive negative input A0

OA0, analog input feedback

P6.2/OA0I1

(SW0A) 65 A9 I/O General-purpose digital I/O pin

OA0, analog input I1

P6.3/A1+/OA1O 64 D9 I/O

General-purpose digital I/O pin

SD16 positive analog input A1

OA1, output

P6.4/A1--/OA1FB 63 A10 I/O

General-purpose digital I/O pin

SD16 positive negative input A1

OA1, analog input feedback

P6.5/OA0I2

(SW0B) 62 B10 I/O General-purpose digital I/O pin

OA0, analog input I2

P6.6/OA1I1

(SW1A) 61 A11 I/O General-purpose digital I/O pin

OA1, analog input I1

P6.7/OA1I2/

SVSIN (SW1B) 59 B12 I/O

General-purpose digital I/O pin

OA1, analog input I2

SVS input

S12 19 L1 OLCD segment output 12

S13 20 M1 OLCD segment output 13

S14 21 M2 OLCD segment output 14

S15 22 M3 OLCD segment output 15

S16 23 L3 OLCD segment output 16

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NO.

NAME 80

113

S17 24 L4 OLCD segment output 17

S18 25 M4 OLCD segment output 18

S19 26 J4 OLCD segment output 19

S22 29 L6 OLCD segment output 22

S23 30 M6 OLCD segment output 23

S24 31 L7 OLCD segment output 24

S25 32 M7 OLCD segment output 25

GND 7E2 Ground. It is used to shield the oscillator. See Note 1.

XIN 8E1 IInput port for crystal oscillator XT1. Standard or watch crystals can be connected.

XOUT 9F1 OOutput port for crystal oscillator XT1. Standard or watch crystals can be connected.

GND 10 F2 Ground. It is used to shield the oscillator. See Note NO TAG.

VREF 60 A12 OInput for an external reference voltage/internal reference voltage output

RST/NMI 74 B5 IReset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).

TCK 73 A5 ITest clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader

start.

TDI/TCLK 71 A6 ITest data input or test clock input. The device protection fuse is connected to TDI/TCLK.

TDO/TDI 70 B7 I/O Test data output port. TDO/TDI data output or programming data input terminal.

TMS 72 B6 ITest mode select. TMS is used as an input port for device programming and test.

XT2OUT 68 A8 OOutput terminal of crystal oscillator XT2

XT2IN 69 A7 IInput port for crystal oscillator XT2

Reserved NA B11,

D6, D7,

D8, E4,

E5, E6,

E7, E8,

E9, F4,

F5, F8,

F9, G4,

G5,G8,

G9, H4,

H5, H6,

H7, H8,

H9, J5,

J6, J7,

J8, L2,

L11

BGA package unused balls. Connection to DVSS/AVSS recommended.

NOTE 1: It is recommended to connect GND externally to DVss.

General-Purpose Register

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-Purpose Register

R10

R11

General-Purpose Register

R14

R15

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

short-form description

CPU

The MSP430 CPU has a 16--bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator, respectively. The

remaining registers are general-purpose

registers.

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

instruction set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats, and Table 2 lists the address

modes.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5

Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)

Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)

Indirect FMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)

Indirect

autoincrement FMOV @Rn+,Rm MOV @R10+,R11 M(R10) —> R11

R10 + 2—> R10

Immediate FMOV #X,TONI MOV #45,TONI #45 —> M(TONI)

NOTE: S = source D = destination

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