Texas Instruments TPS63806EVM Manuale utente

SLVUBJ2–August 2019

TPS63806EVM

User's Guide

SLVUBJ2–August 2019

TPS63806EVM

This user’s guide describes the operation, and use of the TPS63806EVM evaluation module (EVM). The

TPS63806EVM is designed to help the users easily evaluate and test the operation and functionality of the

TPS63806 buck-boost converter. The TPS63806EVM has the output voltage set to 3.3 V. The EVM

operates from 1.3 V to 5.5 V input voltage. Output current can go up to 2 A in buck mode and boost mode.

This document includes setup instructions for the hardware, a schematic diagram, a bill of materials

(BOM), and printed-circuit board (PCB) layout drawings for the evaluation module. Throughout this

document, the abbreviations EVM, TPS63806EVM, and the term evaluation module are synonymous with

the TPS63806, unless otherwise noted.

Figure 1. TPS63806 EVM Picture

Trademarks

All trademarks are the property of their respective owners.

Introduction

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TPS63806EVM

1 Introduction

The Texas Instruments TPS63806 is a highly efficient, single-inductor, internally compensated, buck-boost

converter in a 15-pin, 2.3-mm × 1.4-mm BGA package.

1.1 Background

The TPS63806EVM uses the TPS63806 integrated circuit (IC) and is set to a 3.3 V output and operates

with an input voltage between 1.3 V and 5.5 V.

1.2 Performance Specification

Table 1 provides a summary of the TPS63806EVM performance specifications. All specifications are given

for an ambient temperature of 25°C.

Table 1. Performance Specification Summary

Specification Test Conditions Min Typ Max Unit

Input voltage 1.3 5.5 V

Start-up input voltage 1.8 5.5 V

Output voltage 1.8 5.2 V

Output current VI≥2.2 V , VO= 3.3 V 0 2 A

1.3 Modifications

The printed-circuit board (PCB) for this EVM is designed to accommodate the TPS63806. Extra positions

are available for additional input and output capacitor and feed forward capacitor.

1.3.1 IC U1 Operation

U1 is configured for evaluation of the adjustable-output version. This EVM is set to 3.3 V. Resistors R1

and R2 can be used to set the output voltage between 1.8 V and 5.0 V. See the datasheet for

recommended values.

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Setup

SLVUBJ2–August 2019

TPS63806EVM

2 Setup

This section describes how to properly use the TPS63806EVM.

2.1 Input/Output Connector and Header Descriptions

2.1.1 J1, Pin 1 and 2 – VIN

Positive input connection from the input supply for the EVM.

2.1.2 J1, Pin 3 and 4 – S+/S-

Input voltage sense connections. Measure the input voltage at this point.

2.1.3 J1, Pin 5 and 6 – GND

Vin GND return connection from the input supply for the EVM, common with J2, pin 5 and 6.

2.1.4 J2, Pin 1 and 2 – VOUT

Output voltage connection.

2.1.5 J2, Pin 3 and 4 – S+/S-

Vout Sense and GND Sense low-current sense lines for sampling the output voltage at the output

capacitor.

2.1.6 J2, Pin 5 and 6 – GND

Vout GND return connection for the output voltage, common with J1 pin 5 and 6.

2.1.7 J3 – PG GND

Power Good (PG) test point and GND connection.

2.1.8 JP1 – MODE

Shorting jumper between the center pin MODE and PFM enables automatic transition to power-saving

mode at light-load currents as described in the data sheet; shorting jumper between the center pin MODE

and PWM enables forced PWM mode.

2.1.9 JP2 – ENABLE

Shorting jumper between the center pin EN and ON turns on the unit. Shorting jumper between the center

pin EN and OFF turns the unit off.

2.2 Setup

To operate the EVM, connect an input supply with the positive lead to J1, pins 1 and 2 and negative lead

to J1, pins 5 and 6; connect a load with the positive lead to J2, pins 1 and 2 and the negative lead to J2,

pins 5 and 6; short EN and ON (pins 2 and 3) of JP2 with a shorting jumper.

Board Layout

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3 Board Layout

This section provides the TPS63806EVM board layout and illustrations.

3.1 Layout

Figure 2 through Figure 6 show the board layout for the TPS63806EVM PCB.

Figure 2. Assembly Layer

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Board Layout

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TPS63806EVM

Figure 3. Top Layer Routing

Board Layout

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TPS63806EVM

Figure 4. Signal layer 1

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Board Layout

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TPS63806EVM

Figure 5. Signal Layer 2

Board Layout

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Figure 6. Bottom Layer Routing

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Schematic and Bill of Materials

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TPS63806EVM

4 Schematic and Bill of Materials

This section provides the TPS63806EVM schematic and bill of materials.

4.1 Schematic

Figure 7. Schematic

Schematic and Bill of Materials

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4.2 Bill of Materials

Table 2. TPS63806EVM Bill of Materials

Count RefDes Value Description Size Part Number MFR

1 C1 10 µF CAP, CERM, 10 µF, 6.3 V, +/- 20%, X5R, 0603 603 GRM188R60J106ME84 Murata

1 C5 150 µF CAP, TA, 150 µF, 10 V, +/- 20%, 0.005ohm 7343-31 T530D157M010ATE005 Kemet

2 C6, C7 47 uF CAP, CERM, 47 uF, 6.3 V, +/- 20%, X5R, 0603 603 GRM188R60J476ME15D Murata

1 L1 470 nH Inductor, Shielded, Composite, 470 nH, 3.5 A,

7.6 mOhm 4x4x1.5mm XFL4015-471MEC Coilcraft

1 R1 511 k RES, 511 k, 1%, 0.1 W, 0603 603 Std Std

1 R2 91.0 k RES, 91.0 k, 1%, 0.1 W, 0603 603 Std Std

1 R5 100 k RES, 100 k, 1%, 0.1 W, 0603 603 Std Std

2 R4, R6 1 M RES, 1.00 M, 1%, 0.1 W, AEC-Q200 Grade 0,

0603 603 Std Std

1 U1 - IC, Single Inductor Buck-Boost Converter 2.3x1.4x0.625mm TPS63806YFF TI

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