Texas Instruments TPS7B4255EVM-062 Manuale utente

User’s Guide

TPS7B4255EVM-062 Evaluation Module

ABSTRACT

Figure 1-1. TPS7B4255EVM-062 Evaluation Module

This user's guide describes the operational use of the TPS7B4255EVM-062 evaluation module (EVM) as

a reference design for engineering demonstration and evaluation of the TPS7B4255-Q1 low-dropout linear

regulator (LDO). Included in this user's guide are setup and operating instructions, thermal and layout guidelines,

a printed-circuit board (PCB) layout, a schematic diagram, and a bill of materials (BOM).

Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with the

TPS7B4255EVM-062.

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TPS7B4255EVM-062 Evaluation Module 1

Table of Contents

1 Introduction.............................................................................................................................................................................3

1.1 Before You Begin............................................................................................................................................................... 3

2 TPS7B4255EVM-062 Schematic............................................................................................................................................ 4

3 Setup........................................................................................................................................................................................5

3.1 LDO Input/Output Connector Descriptions.........................................................................................................................5

3.2 Optional Load Transient Input/Output Connector Descriptions..........................................................................................6

3.3 TPS7B4255-Q1 LDO Operation and Component Selection.............................................................................................. 6

3.4 Optional Load Transient Circuit Operation......................................................................................................................... 9

4 Board Layout.........................................................................................................................................................................10

5 Bill of Materials..................................................................................................................................................................... 12

List of Figures

Figure 1-1. TPS7B4255EVM-062 Evaluation Module................................................................................................................. 1

Figure 2-1. Schematic..................................................................................................................................................................4

Figure 3-1. TPS7B4255EVM-062 Turn-On..................................................................................................................................7

Figure 3-2. TPS7B4255EVM-062 With Current Probes Attached............................................................................................... 8

Figure 3-3. TPS7B4255EVM-062 Load Transient Results: 50-μA to 70-mA Load Step..............................................................9

Figure 3-4. TPS7B4255EVM-062 Load Transient Results: 70-mA to 50-μA Load Step..............................................................9

Figure 4-1. Top Assembly Layer and Silkscreen....................................................................................................................... 10

Figure 4-2. Top Layer Routing................................................................................................................................................... 10

Figure 4-3. Internal Layer 1....................................................................................................................................................... 10

Figure 4-4. Internal Layer 2....................................................................................................................................................... 10

Figure 4-5. Internal Layer 3........................................................................................................................................................11

Figure 4-6. Internal Layer 4........................................................................................................................................................11

Figure 4-7. Bottom Layer Routing..............................................................................................................................................11

Figure 4-8. Bottom Assembly Layer and Silkscreen.................................................................................................................. 11

Trademarks

LeCroy™ is a trademark of Teledyne LeCroy.

Kapton® is a registered trademark of DuPont.

All trademarks are the property of their respective owners.

Table of Contents www.ti.com

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1 Introduction

The Texas Instruments' TPS7B4255EVM-062 evaluation module (EVM) helps designers evaluate the operation

and performance of the TPS7B4255-Q1 LDO voltage regulator. As shown in Table 1-1, the TPS7B4255EVM-062

contains one TPS7B4255-Q1 LDO voltage regulator in the SCT-595 package. An optional load transient circuit

is also included to assist the user with high-speed load transient testing. To simplify current measurements, an

input current loop is included.

Table 1-1. Device Information

EVM ORDERABLE NUMBER VOUT PART NAME PACKAGE

TPS7B4255EVM-062 Adjustable - tracking TPS7B4255QDYBRQ1 5-pin SCT-595

1.1 Before You Begin

This evaluation module is not encapsulated and has exposed terminals with voltages that are connected to the

main power supply. The following warnings are noted for the safety of anyone using or working close to the

TPS7B4255EVM-062. Observe all safety precautions.

WARNING

Failure to adhere to these steps or to not heed the safety requirements at each step may lead to

shock, injury, and damage to the hardware. Texas Instruments is not responsible or liable in any way

for shock, injury, or damage caused by negligence or failure to heed advice. If you are not trained

in the proper safety of handling and testing power electronics please do not test this evaluation

module.

CAUTION:

Caution! Do not leave EVM powered when unattended.

HOT SURFACE:

Caution Hot Surface! Contact may cause burns. Do not touch. Please take the proper

precautions when operating.

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TPS7B4255EVM-062 Evaluation Module 3

2 TPS7B4255EVM-062 Schematic

Figure 2-1 shows a schematic for the TPS7B4255EVM-062.

GND

1.00k

R17

DNP

TP1

GND

J3 J4

J10J9

Vin Max = 45V Vout Max = 45V

Iout Max = 70mA

1nF

100V

C20

DNP

VDD

A1 OUTH A2

OUTL B2

IN-

C2 GND B1

IN+

LMG1020YFFR

J21

J20

VDD

J25

GND

50V

10uF

C19

50V

10uF

C18

1.00k

DNP

J15

DNP

50V

0.1uF

C17

154

R12

DNP 154

R13

DNP

154

R11

DNP

154

R10

DNP

1 2

3 4

J17

DNP

GND

ADJ/EN

VIN

ADJ/EN

VOUT

154

DNP

100V

1pF

C14

DNP

R18

DNP

R14

DNP

J26

DNP

1nF

100V

C21

DNP

R19

DNP

J18 J19

J22

DNP

50V

0.015uF

C16

DNP

49.9

R21

GND

J23

TP3

3OUT 4

ADJ/EN

1GND 2

GND 5

TPS7B4255QDYBRQ1

100V

1uF

DNP

100V

1µF

DNP

50V

1uF

DNP

VO 1

FB/NC

2GND 4

GND 5

GND 6

GND 3

7PAD 9

TPS7B8401QWDRBRQ1

VIN

TP2

GND

J14

17.8k

30.0k

48.7k

3.3V

GND

100nF

100V

C10

DNP

10k

DNP

10k

DNP

J11

J12

GND

10µF

25V

C11

GNDGND

Iin Max = 70mA

4.7µF

50V

DNP

1.00

DNP

4.7µF

50V

C15

DNP

1.00

R20

DNP

4.75V Min

5.4V Max

5V Nom

GND

J16

DNP

VIN

GND

J24

100V

1uF

DNP

100V

1uF

DNP

1µF

50V

DNP

VDD

J13

DNP

VIN

GND

VOUTVIN

487

R15

442

R16

1µF

50V

1µF

50V

100nF

100V

C12

10nF

50V

C13 200k

GND

Optional Load

Transient Circuit

Figure 2-1. Schematic

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3 Setup

This section describes the jumpers and connectors on the EVM, and how to properly connect, set up, and use

the TPS7B4255EVM-062. Section 3.1 and Section 3.3 describe the test setup and operation for the TPS7B4255-

Q1 LDO. Section 3.2 and Section 3.4 describe the test setup and operation of the optional load transient circuit.

3.1 LDO Input/Output Connector Descriptions

3.1.1 VIN and GND

VIN and GND are the connection terminals for the input supply. The VIN terminal is the positive connection, and

the GND terminal is the negative (that is, ground) connection.

3.1.2 VOUT and GND

VOUT and GND are the connection terminals for the output load. The VOUT terminal is the positive connection,

and the GND terminal is the negative (that is, ground) connection.

3.1.3 EN

EN is a 3-pin header used to enable or disable the TPS7B84-Q1, which in turn enables the TPS7B4255-Q1.

The center pin of the 3-pin header is tied to the TPS7B84-Q1 EN input. When the 2-pin shunt is placed across

the right two pins of the header, VIN is shorted to EN and the TPS7B84-Q1 is enabled. When the 2-pin shunt is

placed across the left two pins of the header, GND is shorted to EN and the TPS7B84-Q1 is disabled.

If the TPS7B84-Q1 is not to be used to supply the ADJ/EN signal for the TPS7B4255-Q1, remove jumper J11

and use TP1 to drive ADJ/EN directly, or a combination of J5, R1, R3, C10 to configure ADJ/EN to be a function

of the input voltage.

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3.2 Optional Load Transient Input/Output Connector Descriptions

3.2.1 VDD and GND

VDD and GND are the connection terminals for the input supply of the load transient circuit. The VDD terminal is

the positive connection, and the GND terminal is the negative (that is, ground) connection.

3.2.2 J15

J15 is an optional connection for the user to make measurements or apply loads to the output of the LDO.

3.2.3 J18

J18 is an optional connection to insert a damping circuit across the load transient MOSFET drain to source

voltage.

3.2.4 J19

J19 is an optional connection to insert capacitance or additional load across the drain to source of the load

transient MOSFET.

3.2.5 J21

J21 is the connection for the function generator to drive the gate driver device. J21 is terminated by the 50-Ω

resistor, R21.

3.2.6 J22

J22 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET

drain to source voltage.

3.2.7 J23

Short J23 to enable the gate driver.

3.2.8 J26

J26 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET

gate to source voltage.

3.2.9 TP3

TP3 is the test point used to enable the gate driver device. Tie this pin to GND to enable the gate driver.

3.3 TPS7B4255-Q1 LDO Operation and Component Selection

The TPS7B4255EVM-062 evaluation module contains the TPS7B4255-Q1 LDO with input and output capacitors

installed. These three components provide an implementation example, as illustrated by the white boxes

in Figure 3-2. The prepopulated capacitors are sized to ensure the minimum capacitance requirements are

maintained under all normal operating conditions. Optional pads are available to test the LDO with additional

setpoint options, as well as input and output capacitors beyond what is already installed on the EVM.

Setpoint resistors are prepopulated on the TPS7B4255EVM-062 to configure the TPS7B84-Q1 LDO with an

output voltage of 3.3 V, 5 V, or 8 V. With a shunt placed across the pins of jumper J11, the output of the

TPS7B84-Q1 supplies the ADJ/EN pin of the TPS7B4255-Q1. If a different voltage than the TPS7B84-Q1 output

is desired to drive the ADJ/EN pin, remove the shunt from jumper J11 and use a combination of J5, R1, R3, and

C10 to configure the ADJ/EN pin to be a function of the input voltage. Alternatively, TP1 can be used to directly

drive ADJ/EN with an external voltage source.

The TPS7B84-Q1 LDO can be enabled or disabled by using the J14 3-pin header:

• Place a 2-pin shunt across the header to tie VIN to EN to enable the device

• Place a 2-pin shunt across the header to tie GND to EN to disable the device

Alternatively, by connecting an external function generator to TP2 (EN) and a nearby GND post (J9), the

user can enable or disable the TPS7B84-Q1 LDO after VIN is applied. Figure 3-1 illustrates the result of the

TPS7B4255EVM-062 during turn-on. Jumper J14 has a shunt to connect EN of the TPS7B84-Q1 to VIN to

enable the device for this turn-on plot.

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Figure 3-1. TPS7B4255EVM-062 Turn-On

If desired, a current probe can be inserted in the EVM as illustrated in Figure 3-2 to measure the input and

output current. The slots were sized to fit most current probes, such as the LeCroy™ AP015 or CP031 current

probes.

The board layout is designed such that the Iin current probe slot does not detect any current that goes to the

TPS7B84-Q1 circuit or its peripherals during start up or during any other operational mode. Thus, the Iin current

probe slot can be used to isolate and accurately measure current into the TPS7B4255-Q1 solution.

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TPS7B4255EVM-062 Evaluation Module 7

Figure 3-2. TPS7B4255EVM-062 With Current Probes Attached

The user has two options for providing a DC load on the output of the TPS7B4255-Q1. J7 can be used to place

a DC load that flows through the current sense path on the output of the LDO. Alternatively, the J4 (VOUT) and

J10 (GND) banana connectors can be used for external measurements and loading; however, the IOUT loop

does not sense current flowing through these connectors. In cases where very fast transient tests are performed,

ringing may occur on VIN or VOUT as a result of the PCB parasitic inductance. Placing a strip of wire on the

exposed copper in the current path can reduce this ringing. 10 AWG wire can be used as needed. If ringing

persists, install damping networks by adding a series resistor and capacitor in parallel with VIN. Locations where

damping can be installed include C1 and R2, and C15 and R20.

WARNING

Current probe sensors can be tied to GND and must not come into contact with energized

conductors. See the user manual of your current probe for details. If your current probe has this

limitation, use a thin strip of electrical or Kapton® tape to isolate the current sense path from the

current probe.

Optional kelvin sense points are provided using the SMA connectors J1 (VIN) and J2 (VOUT).

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3.4 Optional Load Transient Circuit Operation

The TPS7B4255EVM-062 evaluation module contains an optional high-performance load transient circuit

to allow efficient testing of the TPS7B4255-Q1 LDO load transient performance. To use the optional load

transient circuit, install the correct components in accordance with the application. Modify the input and output

capacitance connected to the TPS7B4255-Q1 LDO to match the expected operating conditions. Determine the

desired peak current to test and modify the parallel resistor combination of R9, R10, R11, R12, and R13 as

shown:

IPeak =VOUT

R9R10 R11 R12 R13

+IDC (1)

The slew rate of the load step can be adjusted by C14, R14, R15, and R16. In this section, only R15 and R16

are adjusted to set the slew rate. For a 0-mA to 70-mA to 0-mA load step, use Table 3-1 to select a value of R15

and R16 that results in the desired rise or fall time.

Table 3-1. Suggested Ramp Rate Resistor Values

R15 R16 Rise, Fall Time

3.4 kΩ 2.1 kΩ 700 ns

1.69 kΩ 1.1 kΩ 350 ns

604 Ω 383 Ω 140 ns

332 Ω 169 Ω 70 ns

121 Ω 69.8 Ω 35 ns

37.4 Ω 0 Ω 14 ns

After the EVM is modified (if needed), connect a power supply to banana connectors J20 (VDD) and J25 (GND)

with a 5-V DC supply and a 1-A DC current limit. As illustrated in Figure 3-3 and Figure 3-4, the TPS7B4255-Q1

transient response is very fast and the output voltage recovers in well under 1 ms after the initial load transient.

Use a pulse-duration limit of 1 ms to prevent excessive heating of the pulsed resistors (R9, R10, R11, R12, and

R13). Configure a function generator for the 50-Ω output, in a 0-V DC to 5-V DC square pulse. If necessary,

burst mode can be configured in the function generator for repetitive, low duty cycle, load transient testing.

Use J14 to short R7 to GND and configure VOUT to be 5-V DC. A 487-Ω resistor is installed on the EVM at R15,

and a 442-Ω resistor is installed on the EVM at R16. These resistors provide approximately 0.5-A/μs slew rate

from both 0 mA to 70 mA and 70 mA to 0 mA. Figure 3-3 and Figure 3-4 provide example test data with R15 =

487 Ω and R16 = 442 Ω. The yellow trace is the input voltage, the red trace is the output voltage, and the blue

trace is the output current. R9, R10, R11, R12, and R13 provide 70 mA of pulsed load. The resulting test data

shows a 50-μA to 70-mA load step on VOUT of the LDO, with only a 1-μF capacitor on the output of the LDO.

Figure 3-3. TPS7B4255EVM-062 Load Transient

Results: 50-μA to 70-mA Load Step

Figure 3-4. TPS7B4255EVM-062 Load Transient

Results: 70-mA to 50-μA Load Step

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TPS7B4255EVM-062 Evaluation Module 9

4 Board Layout

Figure 4-1 through Figure 4-8 illustrate the board layout for the TPS7B4255EVM-062 PCB.

The TPS7B4255EVM-062 dissipates power, which may cause some components to experience an increase in

temperature. The TPS7B4255-Q1 LDO and pulsed resistors R9, R10, R11, R12, and R13 are most at risk of

raising the junction temperature during normal operation. The LDO may become hot to the touch during normal

operation; see the thermal impedance discussion in the TPS7B4255-Q1 data sheet.

Figure 4-1. Top Assembly Layer and Silkscreen Figure 4-2. Top Layer Routing

Figure 4-3. Internal Layer 1 Figure 4-4. Internal Layer 2

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