Alinx AC7021 Manuale utente

ZYNQ7000 FPGA

Core Board

AC7021

User Manual

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Version Record

Version

Date

Release By

Description

Rev 1.0

2019-03-27

Rachel Zhou

First Release

Rev 1.1

2020-09-21

Rachel Zhou

Correct the corresponding pins of B34_L15_N/P.

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Table of Contents

Version Record......................................................................................................................... 2

Part 1: AC7021 Core Board.....................................................................................................4

1.1 Introduction.................................................................................................................. 4

1.2 ZYQN Chip...................................................................................................................6

1.3 DDR3 DRAM............................................................................................................... 9

1.4 QSPI Flash.................................................................................................................12

1.5 eMMC Flash.............................................................................................................. 13

1.6 Clock configuration...................................................................................................15

1.7 USB to serial port......................................................................................................16

1.8 LED............................................................................................................................. 18

1.9 Reset button.............................................................................................................. 19

1.10 JTAGE Interface..................................................................................................... 20

1.11 DIP switch configuration........................................................................................21

1.12 Power........................................................................................................................21

1.13 Structure diagram...................................................................................................24

1.14 Connector pin definition........................................................................................ 24

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Part 1: AC7021 Core Board

1.1 Introduction

The AC7021 (core board model, the same below) core board is an FPGA

development board based on the Zynq chip XC7Z020-2CLG484I of the XILINX

ZYNQ7000 series. The ZYNQ chip's PS system integrates two ARM CortexTM-

A9 processors, AMBA® interconnects, internal memory, external memory

interfaces and peripherals. The ZYNQ FPGA chip contains a wide range of

programmable logic cells, DSP and internal RAM.

The core board uses two SK Hynix DDR3 chips (H5TQ4G63AFR-PBI),

each with a 4Gbit DDR capacity; two DDR chips form a 32-bit data bus width,

and the read and write data clock frequency between ZYNQ FPGA and DDR3

is up to 533Mhz; such a configuration can meet the system's high bandwidth

data processing needs

In order to connect to the carrier board, the four board-to-board connectors

of the core board extend the USB interface of the PS side, the Gigabit Ethernet

interface, the SD card interface and other remaining MIO ports. As well as

almost all IO ports (198) of BANK13, BANK33, BAN34 and BANK35 on the PL

side, the level of IO of BANK33 and BANK34 can be modified by replacing the

LDO chip on the core board to meet the requirements of users with different

level interfaces. For users who need a lot of IOs, this core board will be a good

choice. Moreover, the IOs connection part, the routing between the ZYNQ

FPGA chip and the interface is equal length and differential processing. The

core board size is only 2.36 inch* 2.36 inch, which is very suitable for

secondary development.

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Figure 2-2-1: AC7021Core board Front View

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Figure 2-2-2:AC7021 core board rear view

1.2 ZYQN Chip

The development board uses Xilinx's Zynq7000 series chip, model

XC7Z020-2CLG484I. The chip's PS system integrates two ARM CortexTM-A9

processors, AMBA® interconnects, internal memory, external memory

interfaces and peripherals. These peripherals mainly include USB bus interface,

Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus interface,

UART interface, GPIO, etc. The PS can operate independently and start up at

power up or reset. Figure 2-2-3 detailed the

Overall Block Diagram of the

ZYNQ7000 Chip.

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Figure 2-2-3: Overall Block Diagram of the ZYNQ7000 Chip

The main parameters of the PS system part are as follows:

ARM dual-core CortexA9-based application processor, ARM-v7

architecture, up to 1GHz

32KB level 1 instruction and data cache per CPU, 512KB level 2 cache 2

CPU shares

On-chip boot ROM and 256KB on-chip RAM

External storage interface, support 16/32 bit DDR2, DDR3 interface

Two Gigabit NIC support: divergent-aggregate DMA, GMII, RGMII,

SGMII interface

Two USB2.0 OTG interfaces, each supporting up to 12 nodes

Two CAN2.0B bus interfaces

Two SD card, SDIO, MMC compatible controllers

2 SPIs, 2 UARTs, 2 I2C interfaces

4 groups of 32bit GPIO, 54 (32+22) as PS system IO, 64 connected to

High bandwidth connection within PS and PS to PL

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The main parameters of the PL logic part are as follows:

LogicCells: 85K

Look-up-tables (LUTs):53,200

Flip-flops:106,400

18x25MACCs：220;



BlockRAM：4.9Mb

Two AD converters for on-chip voltage, temperature sensing and up

to 17 external differential input channels, 1MBPS

XC7Z020-2CLG484I chip speed grade is -2, industrial grade, package is

BGA484, pin pitch is 0.024 inch, the specific chip model definition of ZYNQ7000

series is shown in Figure 2-2-4

Figure 2-2-4: The Specific Chip Model Definition of ZYNQ7000 Series

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Figure 2-2-5: TheXC7Z020 chip used on the Core Board

1.3 DDR3 DRAM

The AC7021 core board is equipped with two SK Hynix DDR3 SDRAM

chips (1GB total), model H5TQ4G63AFR-PBI. The bus width of DDR3 SDRAM

is 32 bits in total. DDR3 SDRAM has a maximum operating speed of 533MHz

(data rate 1066Mbps). The DDR3 memory system is directly connected to the

memory interface of the BANK 502 of the ZYNQ Processing System (PS). The

specific configuration of DDR3 SDRAM is shown in Table 2-3-1

Table 2-3-1: DDR3 SDRAM Configuration

The hardware design of DDR3 requires strict consideration of signal

integrity. We have fully considered the matching resistor/terminal resistance,

trace impedance control, and trace length control in circuit design and PCB

design to ensure high-speed and stable operation of DDR3.

Bit Number

Chip Model

Capacity

Factory

U5,U6

H5TQ4G63AFR-PBI

256M x 16bit

SK Hynix

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The hardware connection of DDR3 DRAM is shown in Figure 2-3-1:

Figure 2-3-1: The Schematic part of DDR3 DRAM

Figure 2-3-2: DDR3 DRAM on the Core Board

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