Alinx AC7200 Manuale utente

ARTIX-7 FPGA

Development Board

AC7200

System on Module

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ARTIX-7 SoM FPGA Core Board AC7200 User Manual

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Version Record

Version

Date

Release By

Description

Rev 1.0

2022-04-19

Rachel Zhou

First Release

The English version of the user manual was translated by Shanghai

Tianhui Trading Company. It has not been officially Review by ALINX and is

for reference only. If there are any errors, please send email feedback to

rachel.zhou@aithtech.com for correction.

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Customer Service Information

Wechat/Skype: 15026866269

Technical Email:sup[email protected]

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Table of Contents

Version Record .............................................................................................2

Part 1: AC7200 Core Board Introduction .....................................................4

Part 2: FPGA Chip ........................................................................................6

Part 3: Active Differential Crystal ................................................................. 8

Part 3.1: 200Mhz Active Differential clock ............................................8

Part 3.2: 125Mhz differential clock ....................................................... 9

Part 4: DDR3 DRAM .................................................................................. 11

Part 5: QSPI Flash ..................................................................................... 15

Part 6: LED Light on Core Board ...............................................................17

Part 7: Reset Key .......................................................................................18

Part 8: JTAG Interface ............................................................................... 19

Part 9: Power Interface on the Core Board ............................................... 20

Part 10: Board to Board Connectors ......................................................... 21

Part 11: Power Supply ............................................................................... 28

Part 12: Form Factors ................................................................................ 30

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Part 1: AC7200 Core Board Introduction

AC7200 (core board model, the same below) FPGA core board, it is based

on XILINX's ARTIX-7 series 200T XC7A200T-2FGG484I. It is a

high-performance core board with high speed, high bandwidth and high

capacity. It is suitable for high-speed data communication, video image

processing, high-speed data acquisition, etc.

This AC7200 core board uses two pieces of MICRON's

MT41J256M16HA-125 DDR3 chip, each DDR has a capacity of 4Gbit; two

DDR chips are combined into a 32-bit data bus width, and the read/write data

bandwidth between FPGA and DDR3 is up to 25Gb; such a configuration can

meet the needs of high bandwidth data processing.

The AC7200 core board expands 180 standard IO ports of 3.3V level, 15

standard IO ports of 1.5V level, and 4 pairs of GTP high speed RX/TX

differential signals. For users who need a lot of IO, this core board will be a

good choice. Moreover, the routing between the FPGA chip and the interface is

equal length and differential processing, and the core board size is only 45*55

(mm), which is very suitable for secondary development.

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Figure 1-1: AC7200 Core Board (Front View)

Figure 1-2: AC7200 Core Board (Rear View)

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Part 2: FPGA Chip

As mentioned above, the FPGA model we use is XC7A200T-2FGG484I,

which belongs to Xilinx's Artix-7 series. The speed grade is 2, and the

temperature grade is industry grade. This model is a FGG484 package with

484 pins. Xilinx ARTIX-7 FPGA chip naming rules as below

Figure 2-1: The Specific Chip Model Definition of ARTIX-7 Series

Figure 2-2: FPGA chip on board

The main parameters of the FPGA chip XC7A100T are as follows

Name

Specific parameters

Logic Cells

215360

Slices

33650

CLB flip-flops

269200

Block RAM（kb）

13140

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DSP Slices

740

PCIe Gen2

XADC

1 XADC, 12bit, 1Mbps AD

GTP Transceiver

4 GTP, 6.6Gb/s max

Speed Grade

-2

Temperature Grade

Industrial

FPGA power supply system

Artix-7 FPGA power supplies are VCCINT, VCCBRAM, VCCAUX, VCCO, VMGTAVCC and

VMGTAVTT. VCCINT is the FPGA core power supply pin, which needs to be connected

to 1.0V; VCCBRAM is the power supply pin of FPGA block RAM, connect to 1.0V;

VCCAUX is FPGA auxiliary power supply pin, connect 1.8V; VCCO is the voltage of

each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On

AC7200 FPGA core board, BANK34 and BANK35 need to be connected to

DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK

is 3.3V. The VCCO of BANK15 and BANK16 is powered by the LDO, and can

be changed by replacing the LDO chip. VMGTAVCC is the supply voltage of

the FPGA internal GTP transceiver, connected to 1.0V; VMGTAVTT is the

termination voltage of the GTP transceiver, connected to 1.2V.

The Artix-7 FPGA system requires that the power-up sequence be

VCCINT and VCCBRAM have the same voltage, they can be powered up at

the same time. The order of power outages is reversed. The power-up

sequence of the GTP transceiver is VCCINT, then VMGTAVCC, then

VMGTAVTT. If VCCINT and VMGTAVCC have the same voltage, they can be

powered up at the same time. The power-off sequence is just the opposite of

the power-on sequence.

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Part 3: Active Differential Crystal

The AC7200 core board is equipped with two Sitime active differential

crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main

clock for FPGA and used to generate DDR3 control clock; the other is 125MHz,

model is SiT9102 -125MHz, reference clock input for GTP transceivers.

Part 3.1: 200Mhz Active Differential clock

G1 in Figure 3-1 is the 200M active differential crystal that provides the

development board system clock source. The crystal output is connected to the

BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz

differential clock can be used to drive the user logic in the FPGA. Users can

configure the PLLs and DCMs inside the FPGA to generate clocks of different

frequencies.

Figure 3-1: 200Mhz Active Differential Crystal Schematic

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Figure 3-2: 200Mhz Active Differential Crystal on the Core Board

200Mhz Differential Clock Pin Assignment

Signal Name

FPGA PIN

SYS_CLK_P

SYS_CLK_N

Part 3.2: 125Mhz differential clock

G2 in Figure 3.3 is the 125M active differential crystal oscillator circuit. This

clock is the reference input clock provided to the GTP module inside the FPGA.

The crystal oscillator output is connected to the BANK216 clock pins

MGTREFCLK0P (F6) and MGTREFCLK0N (E6) of the FPGA GTP.

Figure 3-3: 125Mhz Active Differential Crystal Schematic

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Figure 3-4: 125Mhz Active Differential Crystal on the Core Board

125Mhz Differential Clock Pin Assignment

Net Name

FPGA PIN

MGT_CLK0_P

MGT_CLK0_N

Indice

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