Alinx Zynq UltraScale+MPSoC Manuale utente

Zynq UltraScale+MPSoC

FPGA Development

Board

ACU19EG User Manual

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ACU19EG User Manual

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Table of Contents

Version Record................................................................................................................. 2

Table of Contents.............................................................................................................................. 3

Part 1: FPGA Core Board Introduction....................................................................................4

Part 1.1 ZYNQ Chip................................................................................................................4

Part 1.2 DDR4 DRAM............................................................................................................ 6

Part 2.4: QSPI Flash..............................................................................................................14

Part 2.5: eMMC Flash..........................................................................................................16

Part 2.6: Clock configuration ........................................................................................... 17

Part 2.7: Power Supply....................................................................................................... 19

Part 2.8: ACU19EG Core Board Form Factors............................................................ 21

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Part 1: FPGA Core Board Introduction

ACU19EG (core board model name) FPGA core board, ZYNQ chipset is based on

XCZU19EG-2FFVC1760I of XILINX company Zynq UltraScale+ MPSoCs EG Family.

This core board uses 9 Micron DDR4 chips MT40A512M16GE, 5 pcs DDR4 is on

the PS side to form a 72-bit data bus bandwidth and 5GB capacity. 4 DDR4 chip is on

the PL side, which is a 64-bit data bus width and a capacity of 4GB. The high-test

speed of DDR4 SDRAM on the PS side and PL side is 1200MHz (data rate 2400Mbps).

In addition, two 512MBit QSPI FLASH and an 32GB eMMC FLASH chip are also

integrated on the core board.

Eight board-to-board connectors expand the IOs of USB2.0,Gigabit Ethernet, SD

card and other MIOs in PS side; also expand 4 pairs of PS MGT, 48 GTH/GTY

transceivers and almost all IO ports on the PL side (HP I/O:240，HD I/O：96). The core

board size is 80*80 (mm), which is very suitable for secondary development.

ACU19EG Front view of core board

Part 1.1 ZYNQ Chip

The development board uses a series of chips from Xilinx Company's Zynq

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UltraScale+MPSoCs EG series, with the model XCZU19EG-2FFVC1760I. The PS system

of the ZU19EG chip integrates four ARM Cortexs ™- A53 processor, with a speed of

up to 1.3Ghz, supporting Level 2 Cache; In addition, the ZU19EG also includes two

Cortex-R5 processors (with speeds up to 533Mhz).

The ZU19EG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L, and

LPDDR3 storage chips, with rich high-speed interfaces on the PS side such as PCIE

Gen2, USB3.0, SATA 3.1, and DisplayPort; At the same time, it also supports interfaces

such as USB2.0, Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, GPIO, etc. The PL terminal

contains rich programmable logic units, DSP, and internal RAM. The overall block

diagram of the ZU19EG chip is shown in Figures 2-2-1:

Figure 2-2-1 Overall Block Diagram of ZYNQ ZU19EG chip

The main parameters of the PS system part are as follows:

-ARM quad-core Cortex™-A53 processor, speed up to 1.3GHz, each CPU 32KB

level 1 instruction and data cache, 1MB level 2 cache, shared by 2 CPUs。

-ARM dual-core Cortex-R5 processor, speed up to 533MHz, each CPU 32KB

level 1 instruction and data cache, and 128K tightly coupled memory.

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-External Memory Interface, Support 32/64bit DDR4/3/3L、LPDDR4/3 interface.

-Static storage interface, Support NAND, 2xQuad-SPI FLASH.

-High speed connection interface, SupportPCIe Gen2 x4, 2xUSB3.0, Sata 3.1,

DisplayPort, 4x Tri-mode Gigabit Ethernet.

-Ordinary connection interface：2xUSB2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x

I2C, 2x SPI, 4x 32b GPIO.

-Power management: Support division of four power sources Full/Low/PL/Battery

-Encryption algorithm: Support RSA, AES & SHA.

-System monitor: 10 bit 1Mbps AD sampling for temperature and voltage

detection.

The main parameters of the PL logic part are as follows：

- System Logic Cells：1143K；

- CLB flip-flops): 1045K；

- CLBLUTs : 523K；

- Block RAM：34.6Mb；

- Clock Management Unit(CMTs）: 11 pieces

- DSP Slices：1968 pieces

- GTH 16.3Gb/s Transceiver： 44 pieces

The speed level of XCZU19EG-2FFVC1760I chip is -2, industrial grade, and

packaged as FFVC1760.

Part 1.2 DDR4 DRAM

The ACU19EG core board is equipped with 9 Micron (Micron) 1GB DDR4 chips,

model MT40A1G16KD-062E, with 5 DDR4 chips mounted on the PS side, forming a 72

bit data bus bandwidth (supporting ECC), and each DDR chip has a capacity of 1GB.

Mount four DDR4 chips on the PL end to form a 64 bit data bus bandwidth, with each

DDR chip having a capacity of 1GB. The maximum operating speed of the DDR4

SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the four DDR4

storage systems are directly connected to the storage interface of the BANK504 on

the PS. The maximum operating speed of the DDR4 SDRAM on the PL side can reach

1200MHz (data rate 2400Mbps), and four DDR4 chips are connected to the

BANK69,70,71 interfaces of the FPGA. The specific configurations of DDR4 SDRAM on

the PS and PL ends are shown in Table 2-3-1.

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Position

Reference

Part number

Capacity

Factory

U4,U5,U6,U7,U162

MT40A1G16KD-062E

1G x 16bit

Micron

U18,U19,U20,U21

MT40A1G16KD-062E

1G x 16bit

Micron

Table 2-3-1: DDR4 SDRAM Configuration

The hardware design of DDR4 requires strict consideration of Signal integrity. We

have fully considered the matching resistance/terminal resistance, routing impedance

control, and routing equal length control in circuit design and PCB design to ensure

the high-speed and stable operation of DDR4.

The hardware connection method of DDR4 on the PS side is shown in Figure

2-3-1:

Figure 2-3-1: PS DDR4 DRAM block diagram

The block diagram of DDR4 SDRAM on the PL Side is shown in Figure 2-3-2:

Figure 2-3-2: PL DDR4 DRAM block diagram

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PS Side DDR4 DRAM pin assignment:

Signal name

Pin name

Pin number

PS_DDR4_DQS0_N

PS_DDR_DQS_N0_504

BA30

PS_DDR4_DQS0_P

PS_DDR_DQS_P0_504

AY30

PS_DDR4_DQS1_N

PS_DDR_DQS_N1_504

AY33

PS_DDR4_DQS1_P

PS_DDR_DQS_P1_504

AY32

PS_DDR4_DQS2_N

PS_DDR_DQS_N2_504

AT30

PS_DDR4_DQS2_P

PS_DDR_DQS_P2_504

AR30

PS_DDR4_DQS3_N

PS_DDR_DQS_N3_504

AT32

PS_DDR4_DQS3_P

PS_DDR_DQS_P3_504

AR32

PS_DDR4_DQS4_N

PS_DDR_DQS_N4_504

AR40

PS_DDR4_DQS4_P

PS_DDR_DQS_P4_504

AP40

PS_DDR4_DQS5_N

PS_DDR_DQS_N5_504

AK37

PS_DDR4_DQS5_P

PS_DDR_DQS_P5_504

AJ37

PS_DDR4_DQS6_N

PS_DDR_DQS_N6_504

AU41

PS_DDR4_DQS6_P

PS_DDR_DQS_P6_504

AU40

PS_DDR4_DQS7_N

PS_DDR_DQS_N7_504

AL41

PS_DDR4_DQS7_P

PS_DDR_DQS_P7_504

AL40

PS_DDR4_DQS8_N

PS_DDR_DQS_N8_504

AY40

PS_DDR4_DQS8_P

PS_DDR_DQS_P8_504

AY39

PS_DDR4_DQ0

PS_DDR_DQ0_504

AV29

PS_DDR4_DQ1

PS_DDR_DQ1_504

AW30

PS_DDR4_DQ2

PS_DDR_DQ2_504

AW29

PS_DDR4_DQ3

PS_DDR_DQ3_504

AW31

PS_DDR4_DQ4

PS_DDR_DQ4_504

BB31

PS_DDR4_DQ5

PS_DDR_DQ5_504

BB30

PS_DDR4_DQ6

PS_DDR_DQ6_504

BB29

PS_DDR4_DQ7

PS_DDR_DQ7_504

BA31

PS_DDR4_DQ8

PS_DDR_DQ8_504

BB33

PS_DDR4_DQ9

PS_DDR_DQ9_504

BA32

PS_DDR4_DQ10

PS_DDR_DQ10_504

BA33

PS_DDR4_DQ11

PS_DDR_DQ11_504

BB34

PS_DDR4_DQ12

PS_DDR_DQ12_504

AV31

PS_DDR4_DQ13

PS_DDR_DQ13_504

AW32

PS_DDR4_DQ14

PS_DDR_DQ14_504

AV32

PS_DDR4_DQ15

PS_DDR_DQ15_504

AV33

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PS_DDR4_DQ16

PS_DDR_DQ16_504

AN29

PS_DDR4_DQ17

PS_DDR_DQ17_504

AP29

PS_DDR4_DQ18

PS_DDR_DQ18_504

AP30

PS_DDR4_DQ19

PS_DDR_DQ19_504

AP31

PS_DDR4_DQ20

PS_DDR_DQ20_504

AT31

PS_DDR4_DQ21

PS_DDR_DQ21_504

AU30

PS_DDR4_DQ22

PS_DDR_DQ22_504

AU31

PS_DDR4_DQ23

PS_DDR_DQ23_504

AU29

PS_DDR4_DQ24

PS_DDR_DQ24_504

AV34

PS_DDR4_DQ25

PS_DDR_DQ25_504

AU33

PS_DDR4_DQ26

PS_DDR_DQ26_504

AT33

PS_DDR4_DQ27

PS_DDR_DQ27_504

AU34

PS_DDR4_DQ28

PS_DDR_DQ28_504

AN33

PS_DDR4_DQ29

PS_DDR_DQ29_504

AP32

PS_DDR4_DQ30

PS_DDR_DQ30_504

AN32

PS_DDR4_DQ31

PS_DDR_DQ31_504

AN31

PS_DDR4_DQ32

PS_DDR_DQ32_504

AN41

PS_DDR4_DQ33

PS_DDR_DQ33_504

AN42

PS_DDR4_DQ34

PS_DDR_DQ34_504

AP42

PS_DDR4_DQ35

PS_DDR_DQ35_504

AP41

PS_DDR4_DQ36

PS_DDR_DQ36_504

AN39

PS_DDR4_DQ37

PS_DDR_DQ37_504

AR38

PS_DDR4_DQ38

PS_DDR_DQ38_504

AP39

PS_DDR4_DQ39

PS_DDR_DQ39_504

AN38

PS_DDR4_DQ40

PS_DDR_DQ40_504

AL37

PS_DDR4_DQ41

PS_DDR_DQ41_504

AL38

PS_DDR4_DQ42

PS_DDR_DQ42_504

AK38

PS_DDR4_DQ43

PS_DDR_DQ43_504

AK39

PS_DDR4_DQ44

PS_DDR_DQ44_504

AJ36

PS_DDR4_DQ45

PS_DDR_DQ45_504

AL35

PS_DDR4_DQ46

PS_DDR_DQ46_504

AJ35

PS_DDR4_DQ47

PS_DDR_DQ47_504

AK35

PS_DDR4_DQ48

PS_DDR_DQ48_504

AR42

PS_DDR4_DQ49

PS_DDR_DQ49_504

AT41

PS_DDR4_DQ50

PS_DDR_DQ50_504

AT42

PS_DDR4_DQ51

PS_DDR_DQ51_504

AT40

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PS_DDR4_DQ52

PS_DDR_DQ52_504

AV42

PS_DDR4_DQ53

PS_DDR_DQ53_504

AV41

PS_DDR4_DQ54

PS_DDR_DQ54_504

AV39

PS_DDR4_DQ55

PS_DDR_DQ55_504

AV38

PS_DDR4_DQ56

PS_DDR_DQ56_504

AM39

PS_DDR4_DQ57

PS_DDR_DQ57_504

AM38

PS_DDR4_DQ58

PS_DDR_DQ58_504

AM40

PS_DDR4_DQ59

PS_DDR_DQ59_504

AM41

PS_DDR4_DQ60

PS_DDR_DQ60_504

AJ42

PS_DDR4_DQ61

PS_DDR_DQ61_504

AK42

PS_DDR4_DQ62

PS_DDR_DQ62_504

AK40

PS_DDR4_DQ63

PS_DDR_DQ63_504

AK41

PS_DDR4_DQ64

PS_DDR4_DQ64_504

BB40

PS_DDR4_DQ65

PS_DDR4_DQ65_504

BA41

PS_DDR4_DQ66

PS_DDR4_DQ66_504

BA42

PS_DDR4_DQ67

PS_DDR4_DQ67_504

BA40

PS_DDR4_DQ68

PS_DDR4_DQ68_504

AW42

PS_DDR4_DQ69

PS_DDR4_DQ69_504

AW40

PS_DDR4_DQ70

PS_DDR4_DQ70_504

AW41

PS_DDR4_DQ71

PS_DDR4_DQ71_504

AW39

PS_DDR4_DM0

PS_DDR_DM0_504

AY29

PS_DDR4_DM1

PS_DDR_DM1_504

AY34

PS_DDR4_DM2

PS_DDR_DM2_504

AR29

PS_DDR4_DM3

PS_DDR_DM3_504

AR33

PS_DDR4_DM4

PS_DDR_DM4_504

AR39

PS_DDR4_DM5

PS_DDR_DM5_504

AL36

PS_DDR4_DM6

PS_DDR_DM6_504

AU39

PS_DDR4_DM7

PS_DDR_DM7_504

AL42

PS_DDR4_DM8

PS_DDR_DM8_504

AY42

PS_DDR4_A0

PS_DDR_A0_504

BA38

PS_DDR4_A1

PS_DDR_A1_504

BB36

PS_DDR4_A2

PS_DDR_A2_504

BA35

PS_DDR4_A3

PS_DDR_A3_504

BB35

PS_DDR4_A4

PS_DDR_A4_504

BB38

PS_DDR4_A5

PS_DDR_A5_504

AY35

PS_DDR4_A6

PS_DDR_A6_504

AP37

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