Alinx AC7Z100 Manuale utente

ZYNQ7000 FPGA

Development Board

AC7Z100

System on Module

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Version Record

Version

Date

Release By

Description

Rev 1.0

2020-06-28

Rachel Zhou

First Release

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Table of Contents

Version Record......................................................................................... 2

Part 1: AC7Z100 Core Board Introduction ................................................ 4

Part 2: ZYNQ Chip ................................................................................... 5

Part 3: DDR3 DRAM ................................................................................ 8

Part 4: QSPI Flash ................................................................................. 14

Part 5: eMMC Flash ............................................................................... 16

Part 6: Clock Configuration..................................................................... 17

Part 7: LED Light.................................................................................... 20

Part 8: Reset circuit................................................................................ 21

Part 9: Power Supply.............................................................................. 22

Part 10: AC7Z100 Core Board Size Dimension...................................... 24

Part 11: Board to Board Connectors Pin Assignment.............................. 25

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Part 1: AC7Z100 Core Board Introduction

AC7Z100 (core board model, the same below) FPGA core board, ZYNQ

chip is based on XC7Z100-2FFG900 of XILINX company ZYNQ7000 series.

The ZYNQ chip's PS system integrates two ARM CortexTM-A9 processors,

AMBA® interconnects, internal memory, external memory interfaces and

peripherals. The FPGA of the ZYNQ chip contains a wealth of programmable

logic cells, DSP and internal RAM.

The core board uses four Micron 512MB DDR3 chips

MT41J256M16HA-125 for a total capacity of 4GB. Two DDR3s are mounted on

the PS and PL sides, respectively, which form a 32-bit bus width. The DDR3

SDRAM on the PS side can run at up to 533MHz (data rate 1066Mbps), and

the DDR3 SDRAM on the PL side can run at speeds up to 800MHz (data rate

1600Mbps). In addition, two 256MBit QSPI FLASH and 8GB eMMC FLASH

chips are integrated on the core board to boot the storage configuration and

system files.

In order to connect with the carrier board, the four board-to-board

connectors of the core board expand the USB interface, the Gigabit Ethernet

interface, the SD card interface and other remaining IO ports of the PS side;

and also extend the 8-pair high-speed transceiver GTX interface of the ZYNQ,

almost all IO ports (144) on the PL side. The level of IO of BANK12 and

BANK13 can be modified by replacing the LDO chip on the core board to meet

the requirements of different level interfaces of users. For users who need a lot

of IO, this core board will be a good choice. Moreover, the IO connection part,

the routing between the ZYNQ chip and the interface is equal length and

differential processing, and the core board size is only 80*60 (mm), which is

very suitable for secondary development.

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Figure 1-1: AC7Z100 Core Board (Front View)

Figure 1-2: AC7Z100 Core Board (Rear View)

Part 2: ZYNQ Chip

The FPGA core board AC7Z100 uses Xilinx's Zynq7000 series chip,

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module XC7Z100-2FFG900. The chip's PS system integrates two ARM

Cortex™-A9 processors, AMBA® interconnects, internal memory, external

memory interfaces and peripherals. These peripherals mainly include USB bus

interface, Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus

interface, UART interface, GPIO etc. The PS can operate independently and

start up at power on or reset. Figure 2-1 detailed the Overall Block Diagram of

the ZYNQ7000 Chip.

Figure 2-1:

Overall Block Diagram of the ZYNQ7000 Chip

The main parameters of the PS system part are as follows:

ARM dual-core CortexA9-based application processor, ARM-v7

architecture, up to 800MHz

32KB level 1 instruction and data cache per CPU, 512KB level 2 cache

2 CPU shares

On-chip boot ROM and 256KB on-chip RAM

External storage interface, support 16/32 bit DDR2, DDR3 interface

Two Gigabit NIC support: divergent-aggregate DMA, GMII, RGMII,

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SGMII interface

Two USB2.0 OTG interfaces, each supporting up to 12 nodes

Two CAN2.0B bus interfaces

Two SD card, SDIO, MMC compatible controllers

2 SPIs, 2 UARTs, 2 I2C interfaces

54 multi-function IOs that can be configured as normal IO or peripheral

control interfaces

High bandwidth connection within PS and PS to PL

The main parameters of the PL logic part are as follows:

Logic Cells: 444K

Look-up-tables (LUTs): 277440

Flip-flops: 554,800

18x25MACCs：2020



Block RAM

：

26.5Mb

16-channel high-speed GTX transceiver, supporting PCIE Gen2x8;

Two AD converters for on-chip voltage, temperature sensing and up

to 17 external differential input channels, 1MBPS

XC7Z100-2FFG900I

chip speed grade is -2, industrial grade, package is

FGG900, pin pitch is 1.0mm the specific chip model definition of ZYNQ7000

series is shown in Figure 2-2

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Figure 2-2: The Specific Chip Model Definition of ZYNQ7000 Series

Figure 2-3: The XC7Z100 chip used on the Core Board

Part 3: DDR3 DRAM

The FPGA core board AC7Z100 is equipped with four Micron 512MB

DDR3 chips, model MT41J256M16HA-125 (compatible with

MT41K256M16HA-125), in which Two DDR3s are mounted on the PS and PL

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sides respectively. Two DDR3 SDRAMs form a 32-bit bus width. The PS-side

DDR3 SDRAM has a maximum operating speed of 533MHz (data rate

1066Mbps), and two DDR3 memory systems are directly connected to the

memory interface of the BANK 502 of the ZYNQ Processing System (PS). The

PL-side DDR3 SDRAM has a maximum operating speed of 800MHz (data rate

1600Mbps), and two DDR3 memory systems are connected to the BANK33

and BANK34 interfaces of the FPGA. The specific configuration of DDR3

SDRAM is shown in Table 3-1.

Bit Number

Chip Model

Capacity

Factory

U4,U5,U7,U8

MT41J256M16HA-125

256M x 16bit

Micron

Table 3-1: DDR3 SDRAM Configuration

The hardware design of DDR3 requires strict consideration of signal

integrity. We have fully considered the matching resistor/terminal resistance,

trace impedance control, and trace length control in circuit design and PCB

design to ensure high-speed and stable operation of DDR3.

Figure 3-1: The Schematic Part of DDR3 DRAM on the PS side

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Figure 3-2: The Schematic Part of DDR3 DRAM on the PL side

PS side DDR3 DRAM pin assignment:

Signal Name

ZYNQ Pin Name

ZYNQ Pin Number

PS_DDR3_DQS0_P

PS_DDR_DQS_P0_502

C26

PS_DDR3_DQS0_N

PS_DDR_DQS_N0_502

B26

PS_DDR3_DQS1_P

PS_DDR_DQS_P1_502

C29

PS_DDR3_DQS1_N

PS_DDR_DQS_N1_502

B29

PS_DDR3_DQS2_P

PS_DDR_DQS_P2_502

G29

PS_DDR3_DQS2_N

PS_DDR_DQS_N2_502

F29

PS_DDR3_DQS3_P

PS_DDR_DQS_P3_502

L28

PS_DDR3_DQS4_N

PS_DDR_DQS_N3_502

L29

PS_DDR3_D0

PS_DDR_DQ0_502

A25

PS_DDR3_D1

PS_DDR_DQ1_502

E25

PS_DDR3_D2

PS_DDR_DQ2_502

B27

PS_DDR3_D3

PS_DDR_DQ3_502

D25

PS_DDR3_D4

PS_DDR_DQ4_502

B25

PS_DDR3_D5

PS_DDR_DQ5_502

E26

PS_DDR3_D6

PS_DDR_DQ6_502

D26

PS_DDR3_D7

PS_DDR_DQ7_502

E27

PS_DDR3_D8

PS_DDR_DQ8_502

A29

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