Cypress MB966B0 Series Manuale utente

MB966B0 Series

F2MC-16FX 16-Bit Microcontroller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 002-04721 Rev.*A Revised March 3, 2016

MB966B0 series is based on Cypress advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like performance).

The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy migration of F2MC-16LX

Software to the new F2MC-16FX products.

F2MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the

same operation frequency, reduced power consumption and faster start-up time.

For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz

operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going

together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU

voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed.

Features

Technology

0.18m CMOS

CPU

F2MC-16FX CPU

Optimized instruction set for controller applications

(bit, byte, word and long-word data types, 23 different

addressing modes, barrel shift, variety of pointers)

8-byte instruction queue

Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit)

instructions available

System clock

On-chip PLL clock multiplier (1 to 8, 1 when PLL stop)

4MHz to 8MHz crystal oscillator

(maximum frequency when using ceramic resonator

depends on Q-factor)

Up to 8MHz external clock for devices with fast clock input

feature

32.768kHz subsystem quartz clock

100kHz/2MHz internal RC clock for quick and safe startup,

clock stop detection function, watchdog

Clock source selectable from mainclock oscillator, subclock

oscillator and on-chip RC oscillator, independently for CPU

and 2 clock domains of peripherals

The subclock oscillator is enabled by the Boot ROM

program controlled by a configuration marker after a Power

or External reset

Low Power Consumption - 13 operating modes (different

Run, Sleep, Timer, Stop modes)

On-chip voltage regulator

Internal voltage regulator supports a wide MCU supply

voltage range (Min=2.7V), offering low power consumption

Low voltage detection function

Reset is generated when supply voltage falls below

programmable reference voltage

Code Security

Protects Flash Memory content from unintended read-out

DMA

Automatic transfer function independent of CPU, can be

assigned freely to resources

Interrupts

Fast Interrupt processing

8 programmable priority levels

Non-Maskable Interrupt (NMI)

CAN

Supports CAN protocol version 2.0 partA and B

ISO16845 certified

Bit rates up to 1Mbps

32 message objects

Each message object has its own identifier mask

Programmable FIFO mode (concatenation of message

objects)

Maskable interrupt

Disabled Automatic Retransmission mode for Time

Triggered CAN applications

Programmable loop-back mode for self-test operation

USART

Full duplex USARTs (SCI/LIN)

Wide range of baud rate settings using a dedicated reload

timer

Special synchronous options for adapting to different

synchronous serial protocols

LIN functionality working either as master or slave LIN

device

Extended support for LIN-Protocol with 16-byte FIFO for

selected channels to reduce interrupt load

I2C

Up to 400kbps

Master and Slave functionality, 7-bit and 10-bit addressing

A/D converter

SAR-type

8/10-bit resolution

Signals interrupt on conversion end, single conversion

mode, continuous conversion mode,

stop conversion mode, activation by software, external

trigger, reload timers and PPGs

Range Comparator Function

Scan Disable Function

ADC Pulse Detection Function

Source Clock Timers

Three independent clock timers (23-bit RC clock timer,

23-bit Main clock timer, 17-bit Sub clock timer)

Document Number: 002-04721 Rev.*A Page 2 of 74

MB966B0 Series

Hardware Watchdog Timer

Hardware watchdog timer is active after reset

Window function of Watchdog Timer is used to select the

lower window limit of the watchdog interval

Reload Timers

16-bit wide

Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26of peripheral

clock frequency

Event count function

Free-Running Timers

Signals an interrupt on overflow, supports timer clear upon

match with Output Compare (0)

Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28

of peripheral clock frequency

Input Capture Units

16-bit wide

Signals an interrupt upon external event

Rising edge, Falling edge or Both (rising & falling) edges

sensitive

Output Compare Units

16-bit wide

Signals an interrupt when a match with Free-running Timer

occurs

A pair of compare registers can be used to generate an

output signal

Programmable Pulse Generator

16-bit down counter, cycle and duty setting registers

Can be used as 2 × 8-bit PPG

Interrupt at trigger, counter borrow and/or duty match

PWM operation and one-shot operation

Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral

clock as counter clock or of selected Reload timer

underflow as clock input

Can be triggered by software or reload timer

Can trigger ADC conversion

Timing point capture

Start delay

Quadrature Position/Revolution Counter (QPRC)

Up/down count mode, Phase difference count mode,

Count mode with direction

16-bit position counter

16-bit revolution counter

Two 16-bit compare registers with interrupt

Detection edge of the three external event input pins AIN,

BIN and ZIN is configurable

LCD Controller

LCD controller with up to 4COM 36SEG

Internal or external voltage generation

Duty cycle: Selectable from options: 1/2, 1/3 and 1/4

Fixed 1/3 bias

Programmable frame period

Clock source selectable from four options (main clock,

peripheral clock, subclock or RC oscillator clock)

Internal divider resistors or external divider resistors

On-chip data memory for display

LCD display can be operated in Timer Mode

Blank display: selectable

All SEG, COM and V pins can be switched between

general and specialized purposes

Sound Generator

8-bit PWM signal is mixed with tone frequency from 16-bit

reload counter

PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of

peripheral clock

Real Time Clock

Operational on main oscillation (4MHz), sub oscillation

(32kHz) or RC oscillation (100kHz/2MHz)

Capable to correct oscillation deviation of Sub clock or RC

oscillator clock (clock calibration)

Read/write accessible second/minute/hour registers

Can signal interrupts every half

second/second/minute/hour/day

Internal clock divider and prescaler provide exact 1s clock

External Interrupts

Edge or Level sensitive

Interrupt mask bit per channel

Each available CAN channel RX has an external interrupt

for wake-up

Selected USART channels SIN have an external interrupt

for wake-up

Non Maskable Interrupt

Disabled after reset, can be enabled by Boot-ROM

depending on ROM configuration block

Once enabled, cannot be disabled other than by reset

High or Low level sensitive

Pin shared with external interrupt 0

I/O Ports

Most of the external pins can be used as general purpose

I/O

All push-pull outputs (except when used as I2C SDA/SCL

line)

Bit-wise programmable as input/output or peripheral signal

Bit-wise programmable input enable

One input level per GPIO-pin (either Automotive or CMOS

hysteresis)

Bit-wise programmable pull-up resistor

Some pins offer high current output capability for LED

driving.

Built-in On Chip Debugger (OCD)

One-wire debug tool interface

Break function:

•Hardware break: 6 points (shared with code event)

•Software break: 4096 points

Event function

•Code event: 6 points (shared with hardware break)

•Data event: 6 points

•Event sequencer: 2 levels + reset

Execution time measurement function

Trace function: 42 branches

Security function

Document Number: 002-04721 Rev.*A Page 3 of 74

MB966B0 Series

Flash Memory

Dual operation flash allowing reading of one Flash bank

while programming or erasing the other bank

Command sequencer for automatic execution of

programming algorithm and for supporting DMAfor

programming of the Flash Memory

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the automatic algorithm

Erase can be performed on each sector individually

Sector protection

Flash Security feature to protect the content of the Flash

Low voltage detection during Flash erases or writes

Document Number: 002-04721 Rev.*A Page 4 of 74

MB966B0 Series

Contents

1. Product Lineup.................................................................................................................................................................. 6

2. Block Diagram................................................................................................................................................................... 7

3. Pin Assignment................................................................................................................................................................. 8

4. Pin Description.................................................................................................................................................................. 9

5. Pin Circuit Type............................................................................................................................................................... 11

6. I/O Circuit Type................................................................................................................................................................ 14

7. Memory Map.................................................................................................................................................................... 21

8. RAMSTART Addresses................................................................................................................................................... 22

9. User Rom Memory Map For Flash Devices................................................................................................................... 23

10.Serial Programming Communication Interface............................................................................................................ 24

11.Interrupt Vector Table..................................................................................................................................................... 25

12.Handling Precautions..................................................................................................................................................... 29

12.1 Precautions for Product Design................................................................................................................................... 29

12.2 Precautions for Package Mounting.............................................................................................................................. 30

12.3 Precautions for Use Environment................................................................................................................................ 31

13.Handling Devices............................................................................................................................................................ 32

13.1 Latch-up prevention..................................................................................................................................................... 32

13.2 Unused pins handling.................................................................................................................................................. 32

13.3 External clock usage ................................................................................................................................................... 32

13.3.1Single phase external clock for Main oscillator............................................................................................................. 32

13.3.2Single phase external clock for Sub oscillator.............................................................................................................. 33

13.3.3Opposite phase external clock..................................................................................................................................... 33

13.4 Notes on PLL clock mode operation............................................................................................................................ 33

13.5 Power supply pins (Vcc/Vss) ......................................................................................................................................... 33

13.6 Crystal oscillator and ceramic resonator circuit ........................................................................................................... 33

13.7 Turn on sequence of power supply to A/D converter and analog inputs...................................................................... 33

13.8 Pin handling when not using the A/D converter........................................................................................................... 34

13.9 Notes on Power-on...................................................................................................................................................... 34

13.10 Stabilization of power supply voltage........................................................................................................................... 34

13.11 Serial communication.................................................................................................................................................. 34

13.12 Mode Pin (MD) ............................................................................................................................................................ 34

14.Electrical Characteristics ............................................................................................................................................... 35

14.1 Absolute Maximum Ratings......................................................................................................................................... 35

14.2 Recommended Operating Conditions.......................................................................................................................... 37

14.3 DC Characteristics....................................................................................................................................................... 38

14.3.1Current Rating.............................................................................................................................................................. 38

14.3.2Pin Characteristics....................................................................................................................................................... 42

14.4 AC Characteristics....................................................................................................................................................... 44

14.4.1Main Clock Input Characteristics.................................................................................................................................. 44

14.4.2Sub Clock Input Characteristics................................................................................................................................... 45

14.4.3Built-in RC Oscillation Characteristics.......................................................................................................................... 46

14.4.4Internal Clock Timing ................................................................................................................................................... 46

14.4.5Operating Conditions of PLL........................................................................................................................................ 47

14.4.6Reset Input................................................................................................................................................................... 47

14.4.7Power-on Reset Timing................................................................................................................................................ 48

14.4.8USART Timing............................................................................................................................................................. 49

Document Number: 002-04721 Rev.*A Page 5 of 74

MB966B0 Series

14.4.9External Input Timing................................................................................................................................................... 51

14.4.10 I2C Timing................................................................................................................................................................. 52

14.5 A/D Converter.............................................................................................................................................................. 53

14.5.1Electrical Characteristics for the A/D Converter........................................................................................................... 53

14.5.2Accuracy and Setting of the A/D Converter Sampling Time......................................................................................... 54

14.5.3Definition of A/D Converter Terms ............................................................................................................................... 55

14.6 High Current Output Slew Rate................................................................................................................................... 57

14.7 Low Voltage Detection Function Characteristics......................................................................................................... 58

14.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 60

15.Example Characteristics ................................................................................................................................................ 61

16.Ordering Information...................................................................................................................................................... 64

17.Package Dimension........................................................................................................................................................ 65

18.Major Changes ................................................................................................................................................................ 66

Document History................................................................................................................................................................. 73

Document Number: 002-04721 Rev.*A Page 6 of 74

MB966B0 Series

1. Product Lineup

Features

MB966B0

Remark

Product Type

Flash Memory Product

Subclock

Subclock can be set by software

Dual Operation Flash Memory

RAM

128.5KB + 32KB

8KB

MB96F6B5R, MB96F6B5A

Product Options

R: MCU with CAN

A: MCU without CAN

256.5KB + 32KB

16KB

MB96F6B6R

Package

LQFP-100

FPT-100P-M20

DMA

4ch

USART

5ch

LIN-USART 0 to 2/4/5

with automatic LIN-Header

transmission/reception

2ch

LIN-USART 0/1

with 16 byte RX- and

TX-FIFO

I2C

1ch

I2C 0

8/10-bit A/D Converter

27ch

AN 2 to 4/6 to 8/10 to 12/

14 to 31

with Data Buffer

with Range Comparator

Yes

with Scan Disable

Yes

with ADC Pulse Detection

Yes

16-bit Reload Timer (RLT)

5ch

RLT 0 to 3/6

16-bit Free-Running Timer (FRT)

2ch

FRT 0/1

16-bit Input Capture Unit (ICU)

6ch

(5 channels for LIN-USART)

ICU 0/1/4 to 7

(ICU 0/1/4 to 6

for LIN-USART)

16-bit Output Compare Unit (OCU)

4ch

OCU 0 to 3

8/16-bit Programmable Pulse Generator (PPG)

12ch (16-bit) / 16ch (8-bit)

PPG 0 to 7/12 to 15

with Timing point capture

Yes

with Start delay

Yes

with Ramp

Quadrature Position/Revolution Counter

(QPRC)

2ch

QPRC 0/1

CAN Interface

1ch

CAN 0

32 Message Buffers

External Interrupts (INT)

16ch

INT 0 to 15

Non-Maskable Interrupt (NMI)

1ch

Sound Generator (SG)

2ch

SG 0/1

LCD Controller

4COM × 36SEG

COM 0 to 3

SEG 0 to 4/7/11 to 28/30/

33/36 to 45

Real Time Clock (RTC)

1ch

I/O Ports

77 (Dual clock mode)

79 (Single clock mode)

Clock Calibration Unit (CAL)

1ch

Clock Output Function

2ch

Low Voltage Detection Function

Yes

Low voltage detection function

can be disabled by software

Hardware Watchdog Timer

Yes

On-chip RC-oscillator

Yes

On-chip Debugger

Yes

Note:

All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.

It is necessary to use the port relocate function of the general I/O port according to your function use.

Document Number: 002-04721 Rev.*A Page 7 of 74

MB966B0 Series

2. Block Diagram

Interrupt

Controller

DMA

Controller

Peripheral Bus 1 (CLKP1)

Peripheral Bus 2 (CLKP2)

I2C

1ch

I/O Timer 1

FRT1

ICU 4/5/6/7

I/O Timer 0

FRT0

ICU 0/1

OCU 0/1/2/3

16-bit

Reload Timer

0/1/2/3/6

5ch

8/10-bit ADC

27ch

CAN Interface

1ch

USART

5ch

PPG

12ch (16-bit) /

16ch (8-bit)

Real Time

Clock

External

Interrupt

16ch

Vcc

Vss

PPG0, PPG1, PPG3 to PPG7

Peripheral

Bus Bridge

Peripheral

Bus Bridge

16FX Core Bus (CLKB)

TX0

RX0

SIN0 to SIN2, SIN4, SIN5, SIN5_R

SCK0 to SCK2, SCK4, SCK5_R

SOT0 to SOT2, SOT4, SOT5_R

SDA0

SCL0

AN2 to AN4

AN6 to AN8

AN10 to AN12

AN14 to AN31

ADTG

TIN0 to TIN3

TOT0 to TOT3

FRCK0

FRCK1

IN6, IN7

IN4_R, IN5_R, IN7_R

INT0 to INT15

INT1_R to INT7_R

V0 to V3

COM0 to COM3

WOT, WOT_R

TTG0, TTG2 to TTG4, TTG6, TTG7

TTG12 to TTG14

PPG0_R to PPG4_R, PPG12_R, PPG13_R

PPG4_B to PPG7_B, PPG14_B, PPG15_B

IN0

OUT0 to OUT3

FRCK0_R

IN0_R, IN1_R

CKOTX0, CKOTX1, CKOTX1_R

SEG11 to SEG28

DEBUG I/F

OUT0_R, OUT2_R

LCD

controller/

driver

4COM×36SEG

CKOT0_R, CKOT1, CKOT1_R

SEG36 to SEG45

QPRC

2ch

AIN0, AIN1

BIN0, BIN1

ZIN0, ZIN1

Boot ROMMARWatchdog Voltage

Regulator

16FX

CPU Clock &

Mode Controller

Flash

Memory A

NMI

X0, X1

X0A, X1A

RSTX

OCD

AVRL

AVRH

AVss

AVcc

SEG0 to SEG4, SEG7

SEG30, SEG33

Sound

2ch SGA0, SGA1, SGA1_R

SGO0, SGO1, SGO1_R

Generator

Document Number: 002-04721 Rev.*A Page 8 of 74

MB966B0 Series

3. Pin Assignment

(Top view)

(FPT-100P-M20)

*1: CMOS input level only

*2: CMOS input level only for I2C

*3: Please set ROM Configuration Block (RCB) to use the subclock.

Other than those above, general-purpose pins have only Automotive input level.

Vcc

P10_3 / PPG7 / AN31

P10_2 / SCK2 / PPG6 / AN30*1

P10_1 /SOT2 / TOT3 / AN29

P10_0 / SIN2 / TIN3/ INT11 /AN28*1

Vss

Vcc

P09_3 / AN27

P09_2 / AN26

P09_1 / AN25

P09_0 / AN24

P08_7 / AN23 / PPG7_B

P08_6 / AN22 / PPG6_B

P08_5 / AN21

P17_2 / PPG13_R

P17_1 / PPG12_R

P08_4 / AN20

P08_3 / AN19

P08_2 / AN18

P08_1 / AN17

P08_0 / AN16

P05_7 / AN15 / TOT2 / SGA1_R

P05_6 / AN14 / TIN2 / SGO1_R

P05_4 / AN12 / INT2_R/ WOT_R

Vss

Vcc

P00_2 / SEG14 / INT5_R

P00_1 / SEG13 / INT4_R

P00_0 / SEG12 / INT3_R

P12_7 / SEG11 / INT1_R

P12_3 / SEG7 / OUT2_R

P12_0 / SEG4 / IN1_R / BIN1

P11_7 / SEG3 / IN0_R / AIN1

P11_6 /SEG2 / FRCK0_R / ZIN1

P11_5 /SEG1 / PPG4_R

P11_4 /SEG0 / PPG3_R

P11_3 / COM3 / PPG2_R

P11_2 / COM2 / PPG1_R

P11_1 / COM1 / PPG0_R

P11_0 / COM0

RSTX

P04_1 / X1A*3

P04_0 / X0A*3

Vss

P17_0

DEBUG I/F

Vss

P03_7 / INT1 / SIN1 / SEG40*1

P13_0 /INT2 / SOT1 / SEG41

P13_1 / INT3 / SCK1 / SEG42*1

P13_2 / PPG0 / TIN0 / FRCK1 / SEG43

P13_3 / PPG1 / TOT0 /WOT / SEG44

P13_4 / SIN0 / INT6 / SEG45*1

P13_5 / SOT0 /ADTG / INT7

P13_6 / SCK0 / CKOTX0*1

P04_4 / PPG3 / SDA0*2

P04_5 / PPG4 / SCL0*2

P06_2 / AN2 / INT5 / SIN5*1

P06_3 / AN3 / FRCK0

P06_4 / AN4 / IN0 / TTG0 / TTG4

P06_6 / AN6 / TIN1 / IN4_R

P06_7 / AN7 / TOT1 / IN5_R

AVcc

AVRH

AVRL

AVss

P05_0 / AN8

P05_2 / AN10 / OUT2 / SGO1

P05_3 / AN11 / OUT3 / SGA1

Vcc

LQFP - 100

Vss

P00_3 / SEG15 / INT6_R

P00_4 / SEG16 / INT7_R

P00_5 / SEG17 / IN6 / TTG2 / TTG6

P00_6 / SEG18 / IN7 / TTG3 / TTG7

P00_7 / SEG19 / SGO0 / INT14

P01_0 / SEG20 / SGA0

P01_1 / SEG21 / CKOT1 / OUT0

P01_2 /SEG22 / CKOTX1 / OUT1 / INT15

P01_3 / SEG23 / PPG5

P01_4 / SEG24 / SIN4 / INT8*1

P01_5 / SEG25 / SOT4

P01_6 / SEG26 / SCK4 / TTG12*1

P01_7 / SEG27 / CKOTX1_R/ INT9 / TTG13 / ZIN0

P02_0 / SEG28 / CKOT1_R/ INT10 / TTG14 / AIN0

P02_2 / SEG30 / IN7_R/ CKOT0_R/ INT12 / BIN0

P02_5 / SEG33 / OUT0_R/ INT13 / SIN5_R*1

P03_0 / V0 /SEG36 / PPG4_B

P03_1 / V1 /SEG37 / PPG5_B

P03_2 / V2 / SEG38 / PPG14_B/ SOT5_R

P03_3 / V3 /SEG39 / PPG15_B / SCK5_R*1

P03_4 / RX0 / INT4*1

P03_5 / TX0

P03_6 / INT0 / NMI

Vcc 12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

Document Number: 002-04721 Rev.*A Page 9 of 74

MB966B0 Series

4. Pin Description

Pin name

Feature

Description

ADTG

ADC

A/D converter trigger input pin

AINn

QPRC

Quadrature Position/Revolution Counter Unit n input pin

ANn

ADC

A/D converter channel n input pin

AVcc

Supply

Analog circuits power supply pin

AVRH

ADC

A/D converter high reference voltage input pin

AVRL

ADC

A/D converter low reference voltage input pin

AVss

Supply

Analog circuits power supply pin

BINn

QPRC

Quadrature Position/Revolution Counter Unit n input pin

Voltage regulator

Internally regulated power supply stabilization capacitor pin

CKOTn

Clock Output function

Clock Output function n output pin

CKOTn_R

Clock Output function

Relocated Clock Output function n output pin

CKOTXn

Clock Output function

Clock Output function n inverted output pin

CKOTXn_R

Clock Output function

Relocated Clock Output function n inverted output pin

COMn

LCD

LCD Common driver pin

DEBUG I/F

OCD

On Chip Debugger input/output pin

FRCKn

Free-Running Timer

Free-Running Timer n input pin

FRCKn_R

Free-Running Timer

Relocated Free-Running Timer n input pin

INn

ICU

Input Capture Unit n input pin

INn_R

ICU

Relocated Input Capture Unit n input pin

INTn

External Interrupt

External Interrupt n input pin

INTn_R

External Interrupt

Relocated External Interrupt n input pin

Core

Input pin for specifying the operating mode

NMI

External Interrupt

Non-Maskable Interrupt input pin

OUTn

OCU

Output Compare Unit n waveform output pin

OUTn_R

OCU

Relocated Output Compare Unit n waveform output pin

Pnn_m

GPIO

General purpose I/O pin

PPGn

PPG

Programmable Pulse Generator n output pin (16bit/8bit)

PPGn_R

PPG

Relocated Programmable Pulse Generator n output pin (16bit/8bit)

PPGn_B

PPG

Programmable Pulse Generator n output pin (16bit/8bit)

RSTX

Core

Reset input pin

RXn

CAN

CAN interface n RX input pin

SCKn

USART

USART n serial clock input/output pin

SCKn_R

USART

Relocated USART n serial clock input/output pin

SCLn

I2C

I2C interface n clock I/O input/output pin

SDAn

I2C

I2C interface n serial data I/O input/output pin

SEGn

LCD

LCD Segment driver pin

SGAn

Sound Generator

Sound Generator amplitude output pin

SGAn_R

Sound Generator

Relocated Sound Generator amplitude output pin

SGOn

Sound Generator

Sound Generator sound/tone output pin

SGOn_R

Sound Generator

Relocated Sound Generator sound/tone output pin

SINn

USART

USART n serial data input pin

Document Number: 002-04721 Rev.*A Page 10 of 74

MB966B0 Series

Pin name

Feature

Description

SINn_R

USART

Relocated USART n serial data input pin

SOTn

USART

USART n serial data output pin

SOTn_R

USART

Relocated USART n serial data output pin

TINn

Reload Timer

Reload Timer n event input pin

TOTn

Reload Timer

Reload Timer n output pin

TTGn

PPG

Programmable Pulse Generator n trigger input pin

TXn

CAN

CAN interface n TX output pin

LCD

LCD voltage reference pin

Vcc

Supply

Power supply pin

Vss

Supply

Power supply pin

WOT

RTC

Real Time clock output pin

WOT_R

RTC

Relocated Real Time clock output pin

Clock

Oscillator input pin

X0A

Clock

Subclock Oscillator input pin

Clock

Oscillator output pin

X1A

Clock

Subclock Oscillator output pin

ZINn

QPRC

Quadrature Position/Revolution Counter Unit n input pin

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