Epson S1D13706 Manuale utente

Rev. 1.2

S1D13706 Embedded Memory LCD Controller

S5U13706P00C100 Evaluation

Board User Manual

Document Number: X31B-G-021-01.2

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NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission

of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does

not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application

or use in any product or circuit and, further, there is no representation that this material is applicable to products

requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights

is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance

with this material will be free from any patent or copyright infringement of a third party. When exporting the

products or technology described in this material, you should comply with the applicable export control laws and

regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell,

to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the devel-

opment and/or manufacture of weapon of mass destruction or for other military purposes.

All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective

companies.

Evaluation Board/Kit and Development Tool Important Notice

1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or develop-

ment purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished

products.

2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product.

The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any

kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal issue occurs even

during proper and safe use.

3. The part used for this evaluation board/kit or development tool may be changed without any notice.

2Seiko Epson Corporation S5U13706P00C100 Evaluation Board

Rev. 1.2

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S5U13706P00C100 Evaluation Board Seiko Epson Corporation 3

Rev. 1.2

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 12

5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . 16

6.3 S1D13706 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . 16

6.4 Software Adjustable LCD Backlight Intensity Support Using PWM . . . . . . . . . 16

6.5 Passive/Active LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . 17

6.5.1 Buffered LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5.2 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6 External oscillator support for CLKI and CLKI2 . . . . . . . . . . . . . . . . . 17

7 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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4Seiko Epson Corporation S5U13706P00C100 Evaluation Board

Rev. 1.2

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Introduction

S5U13706P00C100 Evaluation Board Seiko Epson Corporation 5

Rev. 1.2

1 Introduction

This manual describes the setup and operation of the S5U13706P00C100 Evaluation

Board. The board is designed as an evaluation platform for the S1D13706 Embedded

Memory LCD Controller.

This document is updated as appropriate. Please check for the latest revision of this

document before beginning any development. The latest revision can be downloaded at

vdc.epson.com.

We appreciate your comments on our documentation. Please contact us via email at

vdc-documentation@ea.epson.com.

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Features

6Seiko Epson Corporation S5U13706P00C100 Evaluation Board

Rev. 1.2

2 Features

Following are some features of the S5U13706P00C100 Evaluation Board:

• 100-pin TQFP S1D13706F00A Embedded Memory LCD Controller with 80K bytes of

embedded SRAM.

• Headers for connecting to various Host Bus Interfaces.

• Configuration options.

• Software adjustable backlight intensity support.

• 4/8-bit 3.3V or 5V single monochrome passive LCD panel support.

• 4/8/16-bit 3.3V or 5V single color passive LCD panel support.

• 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support.

• Direct interface for 18-bit Epson D-TFD LCD panel support.

• Direct interface for 18-bit Sharp HR-TFT LCD panel support.

• Software initiated power save mode.

• Hardware or software Video Invert support.

• External oscillator for CLKI and CLKI2.

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Installation and Configuration

S5U13706P00C100 Evaluation Board Seiko Epson Corporation 7

Rev. 1.2

3 Installation and Configuration

The S5U13706P00C100 is designed to support as many platforms as possible. The

S5U13706P00C100 incorporates a DIP switch and three jumpers which allow both the

evaluation board and S1D13706 LCD controller to be configured for a specified evaluation

platform.

3.1 Configuration DIP Switches

The S1D13706 has configuration inputs (CNF[7:0]) which are read on the rising edge of

RESET#. In order to configure the S1D13706 for multiple Host Bus Interfaces a ten-

position DIP switch (S1) is provided. The following figure shows the location of DIP

switch SW1 on the S5U13706P00C100.

Figure 3-1: Configuration DIP Switch (SW1) Location

DIP Switch - SW1

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Installation and Configuration

8Seiko Epson Corporation S5U13706P00C100 Evaluation Board

Rev. 1.2

The S1D13706 has 8 configuration inputs (CNF[7:0]) which are read on the rising edge of

RESET#. All S1D13706 configuration inputs are fully configurable using a ten position

DIP switch as described below.

Note

1To enable the Hardware Video Invert function the following are required:

• GPIO pins must be enabled (S1-4 closed).

• GPIO0 must be connected to S1-9 (Jumper JP1 set to 1-2).

• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1b.

• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0b.

• Hardware Video Invert Enable bit (REG[70h] bit 5) must be set to 1b.

Table 3-1: Configuration DIP Switch Settings

Switch S1D13706

Signal

Value on this pin at rising edge of RESET# is used to configure:

Closed (On/1) Open (Off/0)

SW1-[3:1] CNF[2:0]

Select host bus interface as follows:

CNF2 CNF1 CNF0 Host Bus Interface

000 SH-4/SH-3

0 0 1 MC68K #1

0 1 0 MC68K #2

0 1 1 Generic #1

1 0 0 Generic #2

101 RedCap2

1 1 0 DragonBall

111 Reserved

Note: The host bus interface is 16-bit.

SW1-4 CNF3 Enable GPIO pins Enable additional pins for D-TFD/HR-TFT

SW1-5 CNF4 Big Endian bus interface Little Endian bus interface

SW1-6 CNF5 WAIT# is active high WAIT# is active low

SW1-[8:7] CNF[7:6]

CLKI to BClk divide select:

CNF7 CNF6 CLKI to BClk Divide Ratio

00 1:1

01 2:1

10 3:1

11 4:1

SW1-91- Hardware Video Invert - invert video data1Hardware Video Invert - normal video data1

SW1-10 - Disable FPGA for non-PCI host Enable FPGA for PCI host

= Required settings when used with PCI Bridge FPGA

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Installation and Configuration

S5U13706P00C100 Evaluation Board Seiko Epson Corporation 9

Rev. 1.2

3.2 Configuration Jumpers

The S5U13706P00C100 has seven jumper blocks which configure various setting on the

evaluation board. The jumper positions for each function are shown below.

JP1 - GPIO0 Connection

JP1 selects whether GPIO0 is connected to SW1-9. SW1-9 is used to enable hardware video

invert on the S1D13706.

When the jumper is on (position 1-2), SW1-9 controls the hardware video invert feature

(default setting).

When the jumper is off, the hardware video invert feature is disabled. This setting must be

used for HR-TFT and D-TFD panels as GPIO0 is required for both panels. For details, refer

to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.

Note

When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no

jumper and JP6 must be set to position 2-3.

Figure 3-2: Configuration Jumper (JP1) Location

Table 3-2: Jumper Summary

Jumper Function Position 1-2 Position 2-3 No Jumper

JP1 GPIO0 Connection

GPIO0 connected to

SW1-9 for hardware video

invert

—

GPIO0 disconnected from

SW1-9 for direct

HR-TFT/D-TFD or GPIO

testing

JP4 GP0 Polarity on H1 Normal (Active High) Inverted (Active Low) —

JP6 LCD Panel Voltage +5V LCDVCC +3.3V LCDVCC —

= recommended settings

JP1

GPIO0 connected GPIO0 disconnected

to SW1-9 from SW1-9

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Installation and Configuration

10 Seiko Epson Corporation S5U13706P00C100 Evaluation Board

Rev. 1.2

JP4 - GPO Polarity on H1

JP4 selects the polarity of the GPO signal available on LCD Connector H1.

Position 1-2 sends the GPO signal directly to H1 (default setting).

Position 2-3 inverts the GPO signal before sending it to H1.

Figure 3-3: Configuration Jumper (JP4) Location

JP6 - LCD Panel Voltage

JP6 selects the voltage level to the LCD panel.

Position 1-2 sets the voltage level to 5.0V.

Position 2-3 sets the voltage level to 3.3V (default setting).

Note

When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no

jumper and JP6 must be set to position 2-3.

Figure 3-4: Configuration Jumper (JP6) Location

JP4

Inverted

Normal

JP6

5.0V 3.3V

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