Freescale Semiconductor MPC850 Manuale utente

MPC850UM/D

Rev. 1, 1/2001

MPC850 Family User’s Manual

Integrated Communications Microprocessor

Supports MPC850

MPC850DE

MPC850SR

MPC850DSL

Freescale Semiconductor

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

[email protected]

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

[email protected]

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

[email protected]

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

Japan

0120 191014 or +81 3 5437 9125

[email protected]

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080

[email protected]

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

[email protected]

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be

provided in Freescale Semiconductor data sheets and/or specifications can and do

vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Semiconductor was negligent regarding the design or manufacture of the part.

III

IND

Part I—Overview

MPC850 Overview

Memory Map

Part II—PowerPC Microprocessor Module

PowerPC Core

PowerPC Core Register Set

MPC850 Instruction Set

Exceptions

Instruction and Data Caches

Memory Management Unit

Instruction Execution Timing

Part III—PowerPC Microprocessor Module

System Interface Unit

Reset

Part IV—Hardware Interface

External Signals

External Bus Interface

Clocks and Power Control

Memory Controller

PCMCIA Interface

III

Part I—Overview

MPC850 Overview

Memory Map

Part II—PowerPC Microprocessor Module

PowerPC Core

PowerPC Core Register Set

MPC850 Instruction Set

Exceptions

Instruction and Data Caches

Memory Management Unit

Instruction Execution Timing

Part III—PowerPC Microprocessor Module

System Interface Unit

Reset

Part IV—Hardware Interface

External Signals

External Bus Interface

Clocks and Power Control

Memory Controller

PCMCIA Interface

VII

GLO

IND

Part V—Communications Processor Module

Communications Processor Module and Timers

Communications Processor

SDMA Channels and IDMA Emulation

Serial Interface

SCC Introduction

SCC UART Mode

SCC HDLC Mode

SCC AppleTalk Mode

SCC Asynchronous HDLC Mode and IrDA

SCC BISYNC Mode

SCC Ethernet Mode

SCC Transparent Mode

IrDA Mode—SCC2 Only

Serial Management Controllers

Serial Peripheral Interface

Universal Serial Bus Controller

C Controller

Parallel I/O Ports

CPM Interrupt Controller

Part VI—Asynchronous Transfer Mode

ATM Overview

Buffer Descriptors and Connection Tables

ATM Parameter RAM

ATM Controller

ATM Pace Control

ATM Exceptions

Interface Conﬁguration

UTOPIA Interface

Part VII—System Debugging and Testing Support

System Development and Debugging

IEEE 1149.1 Test Access Port

Byte Ordering

Serial Communication Performance

Instruction Set Listings

MPC850

MPC850DSL

Glossary

Index

VII

GLO

IND

Part V—Communications Processor Module

Communications Processor Module and Timers

Communications Processor

SDMA Channels and IDMA Emulation

Serial Interface

SCC Introduction

SCC UART Mode

SCC HDLC Mode

SCC AppleTalk Mode

SCC Asynchronous HDLC Mode and IrDA

SCC BISYNC Mode

SCC Ethernet Mode

SCC Transparent Mode

IrDA Mode—SCC2 Only

Serial Management Controllers

Serial Peripheral Interface

Universal Serial Bus Controller

I2C Controller

Parallel I/O Ports

CPM Interrupt Controller

Part VI—Asynchronous Transfer Mode

ATM Overview

Buffer Descriptors and Connection Tables

ATM Parameter RAM

ATM Controller

ATM Pace Controller

ATM Exceptions

Interface Conﬁguration

UTOPIA Interface

MPC850DSL

Part VII—System Debugging and Testing Support

System Development and Debugging

IEEE 1149.1 Test Access Port

Byte Ordering

Serial Communication Performance

Instruction Set Listings

MPC850

Glossary

Index

CONTENTS

Paragraph

Number Title Page

Number

Contents

vii

Part I

Overview

Chapter 1

Overview

1.1 Features............................................................................................................... 1–2

1.2 Overview of Major Components ........................................................................ 1–7

1.2.1 PowerPC Microprocessor Module.................................................................. 1–8

1.2.2 Configuration and Reset ................................................................................. 1–8

1.2.2.1 System Interface Unit (SIU) ....................................................................... 1–8

1.2.2.2 Resets.......................................................................................................... 1–9

1.2.3 MPC850 Hardware Interface ........................................................................ 1–10

1.2.3.1 Signals....................................................................................................... 1–11

1.2.3.2 Clocking and Power Management............................................................ 1–13

1.2.3.3 Memory Controller ................................................................................... 1–14

1.2.4 Communications Processor Module (CPM) ................................................. 1–15

1.2.5 System Debugging and Testing Support ...................................................... 1–17

1.3 Differences between the MPC850 Family and MPC860.................................. 1–17

Chapter 2

Memory Map

Part II

PowerPC Microprocessor Module

Chapter 3

The PowerPC Core

3.1 The MPC850 Core as a PowerPC Implementation............................................. 3-1

3.2 PowerPC Architecture Overview........................................................................ 3-1

3.2.1 Levels of the PowerPC Architecture .............................................................. 3-3

3.3 Features............................................................................................................... 3-4

3.4 Basic Structure of the Core ................................................................................. 3-5

3.4.1 Instruction Flow.............................................................................................. 3-6

3.4.2 Basic Instruction Pipeline ............................................................................... 3-7

3.4.3 Instruction Unit ............................................................................................... 3-7

3.4.3.1 Branch Operations ...................................................................................... 3-7

3.4.3.2 Dispatching Instructions ............................................................................. 3-9

3.5 Register Set ......................................................................................................... 3-9

3.6 Execution Units................................................................................................... 3-9

MPC850 Family User’s Manual

CONTENTS

Paragraph

Number Title Page

Number

3.6.1 Branch Processing Unit ................................................................................ 3-10

3.6.2 Integer Unit ................................................................................................... 3-10

3.6.3 Load/Store Unit............................................................................................. 3-10

3.6.3.1 Executing Load/Store Instructions ........................................................... 3-12

3.6.3.2 Serializing Load/Store Instructions .......................................................... 3-12

3.6.3.3 Store Accesses .......................................................................................... 3-12

3.6.3.4 Nonspeculative Load Instructions ............................................................ 3-13

3.6.3.5 Unaligned Accesses .................................................................................. 3-13

3.6.3.6 Atomic Update Primitives ........................................................................ 3-14

3.7 The MPC850 and the PowerPC Architecture ................................................... 3-14

Chapter 4

PowerPC Core Register Set

4.1 MPC850 Register Implementation ..................................................................... 4-1

4.1.1 PowerPC Registers—User Registers .............................................................. 4-2

4.1.1.1 PowerPC User-Level Register Bit Assignments ........................................ 4-2

4.1.1.1.1 Condition Register (CR)......................................................................... 4-2

4.1.1.1.2 Condition Register CR0 Field Definition............................................... 4-3

4.1.1.1.3 XER ........................................................................................................ 4-3

4.1.1.1.4 Time Base Registers ............................................................................... 4-4

4.1.2 PowerPC Registers—Supervisor Registers .................................................... 4-4

4.1.2.1 DAR, DSISR, and BAR Operation............................................................. 4-5

4.1.2.2 Unsupported Registers................................................................................ 4-6

4.1.2.3 PowerPC Supervisor-Level Register Bit Assignments............................... 4-6

4.1.2.3.1 Machine State Register (MSR)............................................................... 4-6

4.1.2.3.2 Processor Version Register..................................................................... 4-8

4.1.3 MPC850-Specific SPRs.................................................................................. 4-8

4.1.3.1 Accessing SPRs ........................................................................................ 4-11

4.2 Register Initialization at Reset .......................................................................... 4-11

Chapter 5

MPC850 Instruction Set

5.1 Operand Conventions.......................................................................................... 5-1

5.1.1 Data Organization in Memory and Data Transfers......................................... 5-1

5.1.2 Aligned and Misaligned Accesses .................................................................. 5-1

5.2 Instruction Set Summary..................................................................................... 5-2

5.2.1 Classes of Instructions .................................................................................... 5-3

5.2.1.1 Definition of Boundedly Undefined ........................................................... 5-4

5.2.1.2 Defined Instruction Class ........................................................................... 5-4

5.2.1.3 Illegal Instruction Class .............................................................................. 5-4

CONTENTS

Paragraph

Number Title Page

Number

Contents

5.2.1.4 Reserved Instruction Class ......................................................................... 5-5

5.2.2 Addressing Modes .......................................................................................... 5-5

5.2.2.1 Memory Addressing ................................................................................... 5-5

5.2.2.2 Effective Address Calculation .................................................................... 5-6

5.2.2.3 Synchronization .......................................................................................... 5-6

5.2.2.3.1 Context Synchronization ........................................................................ 5-6

5.2.2.3.2 Execution Synchronization..................................................................... 5-7

5.2.2.3.3 Instruction-Related Exceptions............................................................... 5-7

5.2.3 Instruction Set Overview ................................................................................ 5-7

5.2.4 PowerPC UISA Instructions ........................................................................... 5-8

5.2.4.1 Integer Instructions ..................................................................................... 5-8

5.2.4.1.1 Integer Arithmetic Instructions............................................................... 5-8

5.2.4.1.2 Integer Compare Instructions ................................................................. 5-9

5.2.4.1.3 Integer Logical Instructions.................................................................. 5-10

5.2.4.1.4 Integer Rotate and Shift Instructions .................................................... 5-10

5.2.4.2 Load and Store Instructions ...................................................................... 5-11

5.2.4.2.1 Integer Load and Store Address Generation......................................... 5-11

5.2.4.2.2 Register Indirect Integer Load Instructions .......................................... 5-12

5.2.4.2.3 Integer Store Instructions...................................................................... 5-12

5.2.4.2.4 Integer Load and Store with Byte-Reverse Instructions....................... 5-13

5.2.4.2.5 Integer Load and Store Multiple Instructions....................................... 5-13

5.2.4.2.6 Integer Load and Store String Instructions........................................... 5-14

5.2.4.3 Branch and Flow Control Instructions...................................................... 5-14

5.2.4.3.1 Branch Instruction Address Calculation............................................... 5-15

5.2.4.3.2 Branch Instructions............................................................................... 5-15

5.2.4.3.3 Condition Register Logical Instructions............................................... 5-16

5.2.4.4 Trap Instructions....................................................................................... 5-16

5.2.4.5 Processor Control Instructions.................................................................. 5-17

5.2.4.5.1 Move to/from Condition Register Instructions..................................... 5-17

5.2.4.6 Memory Synchronization Instructions—UISA ........................................ 5-17

5.2.5 PowerPC VEA Instructions .......................................................................... 5-19

5.2.5.1 Processor Control Instructions.................................................................. 5-19

5.2.5.2 Memory Synchronization Instructions—VEA ......................................... 5-20

5.2.5.2.1 eieio Behavior....................................................................................... 5-20

5.2.5.2.2 isync Behavior ...................................................................................... 5-20

5.2.5.3 Memory Control Instructions—VEA ....................................................... 5-21

5.2.6 PowerPC OEA Instructions .......................................................................... 5-21

5.2.6.1 System Linkage Instructions..................................................................... 5-22

5.2.6.2 Processor Control Instructions—OEA ..................................................... 5-22

5.2.6.2.1 Move to/from Machine State Register Instructions.............................. 5-22

5.2.6.2.2 Move to/from Special-Purpose Register Instructions........................... 5-22

5.2.6.3 Memory Control Instructions—OEA ....................................................... 5-23

MPC850 Family User’s Manual

CONTENTS

Paragraph

Number Title Page

Number

Chapter 6

Exceptions

6.1 Exceptions........................................................................................................... 6-2

6.1.1 Exception Ordering......................................................................................... 6-3

6.1.2 PowerPC-Defined Exceptions ........................................................................ 6-4

6.1.2.1 System Reset Interrupt (0x00100) .............................................................. 6-5

6.1.2.2 Machine Check Interrupt (0x00200) .......................................................... 6-5

6.1.2.3 DSI Exception (0x00300) ........................................................................... 6-6

6.1.2.4 ISI Exception (0x00400)............................................................................. 6-6

6.1.2.5 External Interrupt Exception (0x00500)..................................................... 6-6

6.1.2.6 Alignment Exception (0x00600) ................................................................ 6-7

6.1.2.6.1 Integer Alignment Exceptions ................................................................ 6-8

6.1.2.7 Program Exception (0x00700).................................................................... 6-9

6.1.2.8 Decrementer Exception (0x00900)........................................................... 6-10

6.1.2.9 System Call Exception (0x00C00) ........................................................... 6-10

6.1.2.10 Trace Exception (0x00D00) ..................................................................... 6-11

6.1.2.11 Floating-Point Assist Exception ............................................................... 6-12

6.1.3 Implementation-Specific Exceptions............................................................ 6-12

6.1.3.1 Software Emulation Exception (0x01000) ............................................... 6-12

6.1.3.2 Instruction TLB Miss Exception (0x01100)............................................. 6-12

6.1.3.3 Data TLB Miss Exception (0x01200)....................................................... 6-13

6.1.3.4 Instruction TLB Error Exception (0x01300) ............................................ 6-13

6.1.3.5 Data TLB Error Exception (0x014000).................................................... 6-14

6.1.3.6 Debug Exceptions (0x01C00–0x01F00) .................................................. 6-15

6.1.4 Implementing the Precise Exception Model................................................. 6-16

6.1.5 Recoverability after an Exception................................................................. 6-17

6.1.6 Exception Latency ........................................................................................ 6-18

6.1.7 Partially Completed Instructions .................................................................. 6-20

Chapter 7

Instruction and Data Caches

7.1 Instruction Cache Organization .......................................................................... 7–2

7.2 Data Cache Organization .................................................................................... 7–4

7.3 Cache Control Registers ..................................................................................... 7–6

7.3.1 Instruction Cache Control Registers ............................................................... 7–6

7.3.1.1 Reading Data and Tags in the Instruction Cache........................................ 7–8

7.3.1.2 IC_CST Commands.................................................................................... 7–9

7.3.1.2.1 Instruction Cache Enable/Disable Commands ....................................... 7–9

7.3.1.2.2 Instruction Cache Load & Lock Cache Block Command ...................... 7–9

7.3.1.2.3 Instruction Cache Unlock Cache Block Command.............................. 7–10

Questo manuale è adatto per i seguenti modelli

Indice

Altri manuali Freescale Semiconductor Hardware per computer

Freescale Semiconductor

Freescale Semiconductor MPC8309 Manuale utente

Freescale Semiconductor

Freescale Semiconductor DSP56366 Manuale utente

Freescale Semiconductor

Freescale Semiconductor TWR-K20D50M Manuale utente

Freescale Semiconductor

Freescale Semiconductor i.MX27 PDK 1.0 Manuale utente

Freescale Semiconductor

Freescale Semiconductor M9328MX21ADSE Manuale utente

Freescale Semiconductor

Freescale Semiconductor TWR-K60N512 Manuale utente

Freescale Semiconductor

Freescale Semiconductor MCF5480 Manuale utente

Freescale Semiconductor

Freescale Semiconductor MSC8144E Manuale utente

Freescale Semiconductor

Freescale Semiconductor MPC8260 PowerQUICC II Family Manuale utente

Freescale Semiconductor

Freescale Semiconductor DSP56374 Manuale utente

Freescale Semiconductor

Freescale Semiconductor MMA9559L Manuale utente

Freescale Semiconductor

Freescale Semiconductor MPC5604P Manuale utente

Freescale Semiconductor

Freescale Semiconductor MPC8569E-MDS-PB Manuale utente

Freescale Semiconductor

Freescale Semiconductor Motorola MMDS0508 Manuale utente

Freescale Semiconductor

Freescale Semiconductor TWR-S12G64 Manuale utente

Freescale Semiconductor

Freescale Semiconductor TWR-MCF51QM Manuale utente

Freescale Semiconductor

Freescale Semiconductor 56F827 Manuale utente

Freescale Semiconductor

Freescale Semiconductor MPC5200B Manuale utente

Freescale Semiconductor

Freescale Semiconductor MC68HC08KH12 Manuale utente

Freescale Semiconductor

Freescale Semiconductor MC68HC908MR16 Manuale utente

Freescale Semiconductor

Freescale Semiconductor MCS08QG8 Manuale utente

Freescale Semiconductor

Freescale Semiconductor ColdFire MCF52210ColdFire MCF52211ColdFire MCF52212ColdFire... Manuale utente

Freescale Semiconductor

Freescale Semiconductor MPC8349EA PowerQUICC II Pro Manuale utente

Freescale Semiconductor

Freescale Semiconductor FRDM-K64F Manuale utente

Manuali Hardware per computer popolari di altre marche

EMC2

EMC2 VNX Series Manuale del proprietario

Panasonic

Panasonic DV0PM20105 Manuale utente

Mitsubishi Electric

Mitsubishi Electric Q81BD-J61BT11 Manuale utente

Gigabyte

Gigabyte B660M DS3H AX DDR4 Manuale utente

Raidon

Raidon iT2300 Manuale utente

National Instruments

National Instruments PXI-8186 Manuale utente

Hauppauge

Hauppauge WinTV-HVR-2250 Manuale utente

Kontron

Kontron CP6002 Manuale utente

Manhattan

Manhattan 702843 Manuale utente

Aphex

Aphex 230 Manuale utente

AMD

AMD Phenom II Manuale operativo

Intel

Intel NUC 12 Pro Manuale utente

dbx

dbx Zone Pro 1260 Manuale utente

Galaxy

Galaxy GHDX2-2430S-24F4D Manuale utente

Intel

Intel AXXRMFBU4 Manuale utente

Kontron

Kontron DIMM-PC/MD Manuale utente

ST X-NUCLEO-SAFEA1B Istruzioni operative

STEINWAY LYNGDORF

STEINWAY LYNGDORF SP-1 Manuale utente