Intersil ISL6294AEVAL1Z Istruzioni per l’uso
1
®ISL6294AEVAL1Z Evaluation Board
Application Manual
Description
The ISL6294AEVAL1Z is an evaluation tool for the
ISL6294A single-cell Li-ion battery charger. The evaluation
tool provides a complete evaluation platform addressing all
data sheet specifications and functionality. The jumpers on
the board facilitate the programming of the charge current,
different charging conditions, and can be used to make other
necessary connections, such as current measurement.
The ISL6294A is a fully integrated single-cell Li-ion battery
charger. The ISL6294A accepts input voltages ranging from
4.5V up to 28V. Due to the high voltage capability, the
components associated with the cradle input circuit on the
evaluation board are good for a 28V supply.
The components assembled in the center square constitute
a complete charger, indicating the space saving advantage
of the typical ISL6294A installation in space-limited
applications.
Pinout ISL6294A
(8 LD DFN)
TOP VIEW
Features
• A Complete Evaluation Platform for the ISL6294A Charger
• The Center Square Suggesting the Space Saving
Advantage of the Typical Components Assembly
• Cradle Input Accepts Voltage up to 28V
• Flexible Power Connectors Each with a Hook and a
Solder Pad Providing Variety to Users
• Convenient Jumpers for Programming the Charge
Current, Charge Mode, and for Current Measurement
• 3.5x2.5 Square Inches Board Size Handy for Evaluation
• Thermal Vias in the Thermal Pad Similar To Customers’
Thermally Enhanced Environment
• On-Board LEDs for Input PPR and CHG State Indication
What is Needed
The following instruments will be needed to perform testing:
• Power supplies:
1) PS1: DC 30V/2A
2) PS2: DC 10V/2A
3) PS3: DC 10V/2A
• DC Electronic load: 20V/2A
• Multimeters
• Function generator
• Oscilloscope
• Cables and wires
Ordering Information
PART NUMBER DESCRIPTION
ISL6294AEVAL1Z Evaluation Board for ISL6294A
2
3
4
1
7
6
5
8
VIN
PPR
CHG
EN
BAT
IREF
IMIN
GND
Application Note
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
AN1457.0May 5, 2009
2AN1457.0
May 5, 2009
Quick Setup Guide (Refer to Figure 1)
DO NOT APPLY POWER UNTIL STEP 5
For Cradle Input
Step 1: Connect a 5V supply PS1 to CRDL input (J1,
upper +) with the current limit set at 1.3A
Step 2: Connect a 3.7V supply PS3 to BAT output (J2,
upper +) with the current limit set at 1.3A
Step 3: Connect a current meter to JP6, as shown in
Figure 1
Step 4: Connect the DC electronic load of 1.2A to BAT
(J2, upper +)
Step 5: Insert a jumper shunt on JP2, JP3, JP4 and JP5,
all other jumpershunts are not installed
Step 6: Turn on Power Supplies and DC electronic load;
adjust the power supply PS3 such that the
voltmeter V2 reads 3.7V
Step 7: Both the red and the green LEDs should be on,
indicating power on and charging condition
Step 8: The current meter I2 should read about 0.6A as
the charging current
Step 9: Insert a jumper shunt on JP7 and the current
meter I2 should read about 1.2A charging
current
Step 10: Remove the jumper shunt on JP3 and apply a
3.3V supply, positive to Pin 1 (at the right) of
JP3, negative to GND
Step 11: Slowly reduce the DC electronic load current
until the green LED turns off; the current meter
I2 should read about 50mA EOC current
FIGURE 1. CONNECTION OF TEST INSTRUMENTS
Application Note 1457
3AN1457.0
May 5, 2009
Description of Jumper Settings
JP1 - Connects the EN pin to a pull-up voltage or GND. The
pull-up voltage is either the BAT voltage (when a shunt is
installed on JP3) or an external 3.3V power source (when
the shunt on JP3 is removed and a +3.3V supply is
connected to pin 1(at the right) of JP3). If there is no shunt
installed on JP1, the EN pin is internally pulled down to logic
LOW, which enables the charger. If a shunt is installed
across the two jumper pins labeled as “Enable”, the EN pin
is driven to logic LOW and the charger is enabled, same as
floating. If the shunt is installed across the two jumper pins
labeled as “Disable” and the pull-up voltage is above 2V, the
EN pin is driven to logic HIGH, which disables the charger.
JP2 - A shunt installed on JP2 connects the input source from
connector J1 to the circuit if input current measurement is not
needed. The shunt can be replaced by a current meter if input
current measurement is needed, as shown in Figure 1.
JP3 - Selects the power source for logic pull-up and the LED
supply. If a shunt is installed, the BAT voltage is selected as
the power source. If the shunt is removed, an external power
supply of +3.3V can be connected from Pin 1 (at the right) to
GND to provide the pull-up and LED supply power. The
purpose is to exclude the extra current through the charger
when characterizing small currents, such as EOC and
quiescent currents.
JP4 - Connect a 243k resistor from IMIN pin to GND for
50mA EOC current.
JP5 - Connect a 20k resistor from IREF to GND for 0.6A
charge current.
JP6 - A shunt installed on JP6 connects the BAT pin to the
output connector J2 if output current measurement is not
needed. The shunt can be replaced by a current meter if
output current measurement is needed as shown in Figure 1.
JP7 - Parallels an additional 20k resistor to the IREF pin
(total RICDL = 10k), the charge current will be increased to
1.2A.
TABLE 1. JUMPER SETTING SUMMARY
JUMPER POSITION FUNCTION
JP1
Shunt on Disable Charger disabled
Shunt on Enable Charger enabled
Shunt not installed Charger enabled
JP2 Shunt installed Connects input source at J1 to VIN
pin
JP3 Shunt installed Select BAT as the pull-up source
JP4 Shunt installed Sets EOC current to 50mA
JP5 Shunt installed Sets charging current to 0.6A, if
shunt on JP7 is not installed
JP6 Shunt installed Connects BAT to J2
JP7 Shunt installed Sets charging current to 1.2A, if
shunt on JP5 is also installed
Application Note 1457
4AN1457.0
May 5, 2009
Board Design
Schematic
FIGURE 2. SCHEMATIC
Application Note 1457
5
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
AN1457.0
May 5, 2009
TABLE 2. ISL6294AEVAL1Z BILL OF MATERIALS
ITEM QTY REFERENCE PART DESCRIPTION PCB
FOOTPRINT PART NUMBER VENDOR
1 1 U1 ISL6294A Charger 2x3 DFN ISL6294A Intersil
2 2 R1, R2 470Ω, 5%, 1/8W Resistor 0805 ERJ-6GEYJ471V Panasonic
5 1 R5 243k, 1%, 1/8W Resistor 0805 ERJ-6ENF2433V Panasonic
6 2 R6, R7 20k, 1% 1/8W Resistor 0805 ERJ-6ENF2002V Panasonic
7 1 C1 4.7µF, 35V, Tantalum 6032 ECS-T1VC475R Panasonic
8 1 C2 0.1µF, 50V, X7R Ceramic 0603 C1608X7R1H104K TDK
9 1 C3 10µF, 6.3V, Tantalum 0603 ECS-T0JY106R Panasonic
10 2 C4, C8 1.0µF, 6.3V, X5R Ceramic 0603 ECJ-1VB0J105K Panasonic
11 1 C6 47µF, 6.3V, X5R Ceramic 1210 ECJ-4YB0J476M Panasonic
12 2 J1, J2 2.54mm Center Header, 2 CKT 22-11-2022 Molex
13 2 CRDL, VBAT Test point, Red 5010 Keystone
14 5 EN, CHG, PPR, IMIN, ICDL Test point, Yellow 5014 Keystone
15 4 GND1, GND2, GND3,
GND4 Test point, Black 5011 Keystone
16 6 JP2, JP3, JP4, JP5, JP6,
JP7 2.54mm header, 2ckt 22-28-4020 Molex
17 1 JP1 2.54mm header, 3ckt 22-28-4030 Molex
18 1 D1 Green LED 0805 SML-LXT0805GW-TR Lumex Opto
19 1 D2 Red LED 0805 SML-LXT0805IW-TR Lumex Opto
Application Note 1457
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