Texas Instruments LP8728EVM Manuale utente

Using the LP8728EVM Evaluation Module

User's Guide

Literature Number: SNVU231

August 2013

Chapter 1

SNVU231–August 2013

Introduction

The Texas Instruments' LP8728EVM evaluation module (EVM) helps designers evaluate the operation

and performance of this device. The LP8728EVM uses the LP8728’s four buck converters to provide 3.3

V, 2.65 V, 1.8 V, and 1.25 V output voltages. Information about output voltage and current ratings of the

LP8728 can also be found in the LP8728 datasheet.

In order to facilitate ease of testing and evaluation of this circuit, the LP8728EVM contains screw-in

terminals for the VIN and all four VOUT connections. Dual connectors are provided for easy four-wire

connection.

For evaluation purposes, the LP8728EVM has been tested over a 4.5 V to 5.5 V input range. Users are

cautioned to evaluate their specific operating conditions and choose components with the appropriate

voltage ratings before designing in LP8728 into a final product.

Figure 1-1. LP8728EVM

2Introduction SNVU231–August 2013

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LP8728

FB_B1

SW_B1 VOUT1

FB_B2

SW_B2 VOUT2

FB_B3

SW_B3

VOUT3

FB_B4

SW_B4 VOUT4

1.5µH

AGND

GND_B1

GND_B2

GND_B3

GND_B4

EN_B1

EN_B2

EN_B3

EN_B4

PG_B1

PG_B2

PG_B3

PG_B4

Micro

Controller

DEFSEL

AVDD

BYP

VIN VIN

VIN_B1

VIN

VIN_B2

1.5µH

VIN

VIN_B3

VIN_B4

VDDIO

1µF

1µF 10µF

10µF

Chapter 2

SNVU231–August 2013

Description of LP8728

The LP8728 is a quad output Power Management Unit, optimized for low power FPGAs, microprocessors,

and DSPs. This device integrates four highly efficient step-down DC/DC converters into one package. All

the converters run at fixed 3.3 MHz switching frequency. Buck converters switching is phase shifted to

minimize the input current spiking.

2.1 Features

• Four High-Efficiency Step-Down DC/DC Converters

– Max output current 1.0 A

– Forced PWM operation

– Soft-start control

– VOUT1 = 3.3 V

– VOUT2 - 1.25 V

– VOUT3 = 1.8 V or 2.65 V (pin selectable)

– VOUT4 = 1.8 V

• Separate Enable Inputs for each Converter Control

• Separate Power Good Outputs for each Converter

• Output Over-Current and Input Over-Voltage Protection

• Over-Temperature Protection

• Under-Voltage Lockout (UVLO)

• 28-pin 0.5 mm Pitch QFN Package

2.2 Applications

• Automotive Systems

Figure 2-1. Typical Application

SNVU231–August 2013 Description of LP8728

Chapter 3

SNVU231–August 2013

LP8728EVM Setup

Figure 3-1 shows the LP8728EVM with input and output connectors and main components on the board.

Input power supply is connected to VIN connectors. Two connectors are provided for easy 4-wire

connection. A force line should be connected to connector X1 terminals VIN and GND. Sense wires

should be connected to connector X2 terminals VINS and GNDS. If a two-wire connection is used, wires

should be connected to connector X1 VIN and GND only. Input voltage needs to be set between 4.5 V to

5.5 V.

Two connectors are also provided for each buck output. This is useful, for example, when connecting the

source meter in 4-wire mode for accurate IOUT vs VOUT measurement. Two output terminals are

connected in parallel so either one can be used for sense or force lines.

Connector X3 terminals VDDIOX and GND can be used to connect separated pull-up voltage for the

EN_Bx and DEFSEL pins. If separated pull-up voltage is not desired, input pins can be pulled up to VIN

voltage. Pull-up voltage is selected by changing the shunt position on the J2 terminal. Connecting shunt

between VDDIO and VDDIOX selects VDDIOX as the pull-up voltage. Connecting a shunt between

VDDIO and AVDD selects VIN as the pull-up voltage.

Extra test points are placed close to the buck output capacitors for convenient probe points for an

oscilloscope. Similar test points are also placed close to each input voltage pin (VIN_Bx and AVDD).

Figure 3-1. Evaluation Board Connectors and Setup

4LP8728EVM Setup SNVU231–August 2013

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Chapter 4

SNVU231–August 2013

Board Layout

Figure 4-1. Layer 1 Top (Signal)

Figure 4-2. Layer 2 (GND) (Picture in reverse colors)

SNVU231–August 2013 Board Layout

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Figure 4-3. Layer 2 (GND / VIN)

Figure 4-4. Layer 4 Bottom (Signal)

6Board Layout SNVU231–August 2013

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Figure 4-5. Close-up of the LP8728 and Main External Components

SNVU231–August 2013 Board Layout

Chapter 5

SNVU231–August 2013

Board Stackup

Figure 5-1. Evaluation Board Stackup

Details:

• 4-layer board FR4

• Top layer 1 - copper, 35µm

• Prepreg 0.1 mm

• Internal Layer 2, 35 µm

• Core 0.7 mm

• Ground plane Layer 3, 35 µm

• Prepreg 0.1 mm

• Bottom Layer 4 - copper, 35 µm

• Surface finish immersion gold

8Board Stackup SNVU231–August 2013

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Chapter 6

SNVU231–August 2013

Controls

The LP8728 has four enable pins (EN_Bx). When any of the enable pins are pulled high, the device

activates and starts up corresponding the buck converter (EN_B1 controls buck1, EN_B2 controls buck2,

etc). When all EN_Bx pins are low, the device goes to shutdown mode.

DEFSEL is used to select buck 3 output voltage. If the DEFSEL pin is pulled high, buck 3 output voltage is

set to 2.65 V. If DEFSEL pin is set low, buck 3 output voltage is set to 1.8 V

EN_Bx pins and the DEFSEL pin have internal pull-down resistors (500 kΩ) which will set the state to low

when the EN input is floating.

Power good outputs indicate the status of each buck converter. Once buck output voltage reaches 96%

(typ) of the desired output voltage, the power good pin is pulled high. If output voltage drops below 93%

(typ) of desired output voltage due to, for example, an overload condition, the corresponding power good

pin is set low.

6.1 LP8728EVM Control Interface

Figure 6-1. LP8728EVM Control Pins

All LP8728 digital input and out signals are routed to 20-pin connector (J3) pins. Pins closer to PCB edge

go straight to the LP8728 digital pins. These pins can be used to connect LP8728 pins to any external

source (signal generators, external controllers, etc). For simple enable / disable operation pull-up resistors

are connected to adjacent pins of the digital inputs. This allows enabling the bucks by setting shunts

between the J3 pins.

Indicator LEDs are provided for power good signals PG_Bx. LEDs are connected between VIN and

PG_Bx pin so the LED illuminates when power good signal is low (buck is disabled or output voltage out

of regulation). Indicator LEDs can be disconnected from the PG_Bx pins by removing the shunts form

connector J3.

SNVU231–August 2013 Controls

Chapter 7

SNVU231–August 2013

Evaluation Board Schematic

Figure 7-1. Evaluation Board Schematic

10 Evaluation Board Schematic SNVU231–August 2013

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