Texas Instruments ADC DJ Series Manuale utente

ADCxxDJxx00 Evaluation Module

User's Guide

Literature Number: SLAU701A

May 2017–Revised January 2018

2SLAU701A–May 2017–Revised January 2018

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Contents

1 Introduction......................................................................................................................... 4

2 Equipment........................................................................................................................... 6

2.1 Evaluation Board Feature Identification Summary ...................................................................... 6

2.2 Required Equipment......................................................................................................... 7

3 Setup Procedure.................................................................................................................. 8

3.1 Install the High Speed Data Converter (HSDC) Pro Software......................................................... 9

3.2 Install the Configuration GUI Software.................................................................................... 9

3.3 Connect the EVM and TSW14J57EVM................................................................................... 9

3.4 Connect the Power Supplies to the Boards (Power Off) ............................................................... 9

3.5 Connect the Signal Generators to the EVM (*RF Outputs Disabled Until Directed)................................ 9

3.6 Turn On the TSW14J57EVM Power and Connect to the PC ........................................................ 10

3.7 Turn On the ADCxxDJxx00EVM Power Supplies and Connect to the PC ......................................... 10

3.8 Turn On the Signal Generator RF Outputs ............................................................................. 10

3.9 Open the ADCxxDJxx00EVM GUI and Program the ADC and Clocks ............................................. 10

3.10 Calibrate the ADC Device on the EVM.................................................................................. 12

3.11 Open the HSDC Software and Load the FPGA Image to the TSW14J57EVM.................................... 13

3.12 Capture Data Using the HSDC Pro Software .......................................................................... 13

4 Device Configuration .......................................................................................................... 16

4.1 Supported JESD204B Device Features................................................................................. 16

4.2 Tab Organization........................................................................................................... 16

4.3 Low-Level Control.......................................................................................................... 17

5 Troubleshooting the ADCxxDJxx00EVM................................................................................ 18

A References ........................................................................................................................ 19

A.1 Technical Reference Documents......................................................................................... 19

A.2 TSW14J57EVM Operation................................................................................................ 19

A.3 TSW14J56EVM Operation................................................................................................ 19

B HSDC Pro Settings for Optional ADC Device Configuration..................................................... 20

B.1 Changing the Number of Frames per Multi-Frame (K)................................................................ 20

B.2 Customizing the EVM for Optional Clocking Support ................................................................. 20

C Signal Routing .................................................................................................................. 23

Revision History.......................................................................................................................... 23

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SLAU701A–May 2017–Revised January 2018

List of Figures

1-1. EVM Orientation ............................................................................................................. 5

2-1. EVM Feature Locations..................................................................................................... 6

3-1. EVM Test Setup.............................................................................................................. 8

3-2. Configuration GUI EVM Tab.............................................................................................. 11

3-3. Configuration GUI ADC Control .......................................................................................... 12

3-4. High Speed Data Converter Pro (HSDC) GUI.......................................................................... 14

3-5. Additional Device Parameters Dialog Box .............................................................................. 15

4-1. Low-Level Register Control Tab ......................................................................................... 17

B-1. ADC12DJxx00EVM Clocking System Block Diagram................................................................. 20

B-2. External LMKCLK Configuration ......................................................................................... 21

B-3. External DevCLK EVM Configuration.................................................................................... 22

List of Tables

4-1. Supported and Non-Supported Features of the JESD204B Device................................................. 16

4-2. Low-Level Controls......................................................................................................... 17

5-1. Troubleshooting ............................................................................................................ 18

C-1. ADCxxDJxx00EVM Signal Routing ..................................................................................... 23

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Introduction

K&L Microwave is a trademark of K&L Microwave.

Microsoft, Windows are registered trademarks of Microsoft Corporation.

Rohde & Schwarz is a registered trademark of Rohde & Schwarz GmbH & Co..

Trilithic is a trademark of Trilithic, Inc..

Chapter 1

SLAU701A–May 2017–Revised January 2018

Introduction

The ADCxxDJxx00EVM is an evaluation board used to evaluate the ADCxxDJxx00 family (ADC08DJ3200,

ADC12DJ2700 and ADC12DJ3200) of analog-to-digital converters (ADC) from Texas Instruments. The

ADCxxDJxx00 devices are dual-channel, 8 or 12-bit ADCs, capable of operating at sampling rates up to

3.2 Giga-samples per second (GSPS) in dual channel mode or 6.4 GSPS in single channel mode. The

ADCxxDJxx00EVM device output data is transmitted over a standard JESD204B high-speed serial

interface. This evaluation board also includes the following important features:

• Transformer-coupled signal input network allowing a single-ended signal source from 500 kHz to

9 GHz

• The LMX2582 clock synthesizer generates the ADC sampling clock

• The LMK04828 and LMX2582 onboard system clock generator generates SYSREF and FPGA

reference clocks for the high-speed serial interface

• Transformer-coupled clock input network to test the ADC performance with an external low-noise clock

source

• LM95233 temperature sensor

• High-speed serial data output over a High Pin Count FMC+ interface connector

NOTE: To improve signal routing quality, serial lane polarity is inverted with respect to the standard

FMC VITA-57 signal mapping. Signal mapping and polarity is shown in Table C-1).

• Device register programming through USB connector and FTDI USB-to-SPI bus translator

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SLAU701A–May 2017–Revised January 2018

Introduction

Figure 1-1. EVM Orientation

The digital data from the ADCxxDJxx00EVM board is quickly and easily captured with the TSW14J57EVM

or TSW14J56EVM data capture boards.

NOTE: The TSW14J56EVM cannot be used for JMODES that use 16 data lanes, or serial rates

above 12 Gbps.

The TSW14J57EVM captures the high-speed serial data, decodes the data, stores the data in memory,

and then uploads it to a connected PC through a USB interface for analysis. The High-Speed Data

Converter Pro (HSDC Pro) software on the PC communicates with the hardware and processes the data.

With proper hardware selection in the HSDC Pro software, the TSW14J57 device is automatically

configured to support a wide range of operating speeds of the ADC12DJ3200EVM, but the device may not

cover the full operating range of the ADC device. Serial data rates of 12.8 Gbps down to 1 Gbps are

supported.

In the following sections of this document, the ADCxxDJxx00 evaluation board is referred to as the EVM

and the ADCxxDJxx00 device is referred to as the ADC device.

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Equipment

Chapter 2

SLAU701A–May 2017–Revised January 2018

Equipment

This section describes how to setup the EVM on the bench with the proper equipment to evaluate the full

performance of the ADC device.

2.1 Evaluation Board Feature Identification Summary

Figure 2-1. EVM Feature Locations

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Required Equipment

SLAU701A–May 2017–Revised January 2018

Equipment

2.2 Required Equipment

The following equipment and documents are included in the EVM evaluation kit:

• Evaluation board (EVM)

• Mini-USB cable

• Power cable

The following equipment is not included in the EVM evaluation kit, but is required for evaluation of this

product:

• TSW14J57EVM or TSW14J56EVM data capture board and related items

• High-Speed Data Converter Pro software

• PC computer running Microsoft®Windows®XP, 7, or 8

• One low-noise signal generator for analog input. TI recommends the following generators:

– Keysight E8663D

– Rohde & Schwarz®SMA100A

• Bandpass filter for analog input signal (1910 MHz or desired frequency). The following filters are

recommended:

– Bandpass filter, greater than or equal to 60-dB harmonic attenuation, less than or equal to 5%

bandwidth, greater than 18-dBm power, less than 5-dB insertion loss

– Trilithic™ 5VH-series tunable BPF

– K&L Microwave™ BT-series tunable BPF

– TTE KC6 or KC7-series fixed BPF

• Signal-path cables, SMA or BNC (or both SMA and BNC)

By default, the ADCxxDJxx00EVM has an onboard clocking solution. A few small board modifications

enable external clocking. If external clocking is used, the following equipment is recommended.

• Two low-noise signal generators. TI recommends similar models to the analog input source.

• A bandpass filter for the DEVCLK input. TI recommends a filter similar to the analog-input path filter.

NOTE: The clock source used to drive the LMK04828 (labeled LMKCLK) must be equal in frequency

to the ADC sampling clock (labeled DEVCLK). The clock generators must be frequency-

locked using a common 10-MHz reference.

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Setup Procedure

Chapter 3

SLAU701A–May 2017–Revised January 2018

Setup Procedure

Figure 3-1. EVM Test Setup

NOTE: The HSDC Pro software must be installed before connecting the TSW14J57EVM to the PC

for the first time.

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Install the High Speed Data Converter (HSDC) Pro Software

SLAU701A–May 2017–Revised January 2018

Setup Procedure

3.1 Install the High Speed Data Converter (HSDC) Pro Software

Download the most recent version of the HSDC Pro software from www.ti.com/tool/dataconverterpro-sw.

Follow the installation instructions to install the software.

3.2 Install the Configuration GUI Software

1. Download the Configuration GUI software from the EVM tool folder at ADC12DJxx00 GUI .

2. Extract files from the .zip file.

3. Run the executable file (setup.exe), and follow the instructions.

3.3 Connect the EVM and TSW14J57EVM

With the power off, connect the ADCxxDJxx00EVM to the TSW14J57EVM through the FMC connector as

shown in Figure 3-1. Ensure that the standoffs provide the proper height for robust connector connections.

3.4 Connect the Power Supplies to the Boards (Power Off)

1. Confirm that the power switch on the TSW14J57EVM is in the off position. Connect the power cable to

a 12-V DC (minimum 2 A) power supply. Ensure the proper supply polarity by confirming that the outer

surface of the barrel connector is GND and the inner portion of the connector is 12 V. Connect the

power cable to the EVM power connector.

2. Confirm that the power switch on the ADCxxDJxx00EVM is in the off position. Connect the power

cable to a 5-V DC (minimum 3 A) power supply. Ensure the proper supply polarity by confirming that

the outer surface of the barrel connector is GND and the inner portion of the connector is 5 V. Connect

the power cable to the EVM power connector.

CAUTION

Ensure the power connections to the EVMs are the correct polarity.

Failure to do so may result in immediate damage

Ensure the 12-V power supply is connected to the TSW14J57EVM and not

the ADCxxDJxx00EVM. Providing the ADCxxDJxx00EVM with 12 V may

result in immediate damage

Leave the power switches in the off position until directed later.

3.5 Connect the Signal Generators to the EVM (*RF Outputs Disabled Until Directed)

1. Connect a signal generator to the VIN input of the ADCxxDJxx00EVM through a bandpass filter and

attenuator at the SMA connector. This must be a low-noise signal generator. TI recommends a

Trilithic-tunable bandpass filter to filter the signal from the generator. Configure the signal generator for

1910 MHz, 0 dBm.

If External Clocking is Used (Optional)

a. Connect a signal generator to the DEVCLK input of the EVM through a bandpass filter. This signal

generator must be a low-noise signal generator. TI recommends a Trilithic-tunable bandpass filter

to filter the signal coming from the generator. Configure the signal generator for the desired clock

frequency in the range of 0.8 to 3.2 GHz. For best performance when using an RF signal

generator, the power input to the CLK SMA connector must be 9 dBm (2.2 Vpp into 50 Ω). The

signal generator must increase above 9 dB by an amount equal to any additional attenuation in the

clock signal path, such as the insertion loss of the bandpass filter. For example, if the filter

insertion loss is 2 dB, the signal generator must be set to 9 dBm + 2 dB = 11 dBm.

b. Connect a signal generator to the LMKCLK input of the EVM through a bandpass filter. Configure

the signal generator for the desired clock frequency in the range of 0.8 to 3.2 GHz. Set the output

power to approximately 6–9 dBm.

Turn On the TSW14J57EVM Power and Connect to the PC

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Setup Procedure

NOTE: 1. The LMKCLK frequency must be equal to the frequency of the DEVCLK.

2. Ensure that the DEVCLK and LMKCLK sources are frequency-locked using a common

10-MHz reference to ensure functionality. Frequency locking the input signal generator to

the other generators can also be done if coherent sampling is desired.

3. Do not turn on the RF output of any signal generator at this time.

4. When using the ADC in single-input mode, the device uses both edges of DEVCLK for

sampling.

3.6 Turn On the TSW14J57EVM Power and Connect to the PC

1. Turn on the power switch of the TSW14J57EVM.

2. Connect a mini-USB cable from the PC to the TSW14J57EVM.

3. If this is the first time connecting the TSW14J57EVM to the PC, follow the on-screen instructions to

automatically install the device drivers. See the TSW14J57EVM user's guide (SLWU092) for specific

instructions.

3.7 Turn On the ADCxxDJxx00EVM Power Supplies and Connect to the PC

1. Turn on the 5-V power supply to power up the EVM.

2. Connect the EVM to the PC with the mini-USB cable.

3.8 Turn On the Signal Generator RF Outputs

Turn on the RF signal output of the signal generator connected to VIN. If external clocking is used, turn on

the RF signal outputs connected to DEVCLK and LMKCLK.

3.9 Open the ADCxxDJxx00EVM GUI and Program the ADC and Clocks

The Device Configuration GUI is installed separately from the HSDC Pro installation and is a stand-alone

GUI.

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