Epson S5U13A05P00C100 Manuale utente

Rev. 1.02

S1D13A05 LCD/USB Companion Chip

S5U13A05P00C100 Evaluation

Board User Manual

Document Number: X40A-G-014-01.02

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission

of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does

not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application

or use in any product or circuit and, further, there is no representation that this material is applicable to products

requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights

is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance

with this material will be free from any patent or copyright infringement of a third party. When exporting the

products or technology described in this material, you should comply with the applicable export control laws and

regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell,

to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the devel-

opment and/or manufacture of weapon of mass destruction or for other military purposes.

All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective

companies.

Evaluation Board/Kit and Development Tool Important Notice

1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or develop-

ment purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished

products.

2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product.

The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any

kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal issue occurs even

during proper and safe use.

3. The part used for this evaluation board/kit or development tool may be changed without any notice.

2Seiko Epson Corporation S5U13A05P00C100 Evaluation Board

Rev. 1.02

S5U13A05P00C100 Evaluation Board Seiko Epson Corporation 3

Rev. 1.02

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 12

5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . 16

6.3 S1D13A05 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . 16

6.4 Software Adjustable LCD Backlight Intensity Support Using PWM . . . . . . . . . 16

6.5 LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5.1 LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5.2 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5.3 TFT Type 3 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . 18

6.6 USB Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.6.1 USB IRQ Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.7 External oscillator support for CLKI and CLKI2 . . . . . . . . . . . . . . . . . 18

6.8 External oscillator support for USBCLK . . . . . . . . . . . . . . . . . . . . 18

7 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

11 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4Seiko Epson Corporation S5U13A05P00C100 Evaluation Board

Rev. 1.02

Introduction

S5U13A05P00C100 Evaluation Board Seiko Epson Corporation 5

Rev. 1.02

1 Introduction

This manual describes the setup and operation of the S5U13A05P00C100 Evaluation

Board. The board is designed as an evaluation platform for the S1D13A05 LCD/USB

Companion Chip.

This document is updated as appropriate. Please check for the latest revision of this

document before beginning any development. The latest revision can be downloaded at

vdc.epson.com.

We appreciate your comments on our documentation. Please contact us via email at

vdc-document[email protected].com.

Features

6Seiko Epson Corporation S5U13A05P00C100 Evaluation Board

Rev. 1.02

2 Features

Following are some features of the S5U13A05P00C100 Evaluation Board:

• 121-pin PFBGA S1D13A05 Embedded Memory LCD Controller with 256K bytes of

embedded SRAM.

• PCI bus operation through onboard PCI bridge.

• CPU/Bus interface header strips for non-PCI bus operation.

• Configuration options.

• Software adjustable backlight intensity support using PWMOUT.

• 4/8-bit 3.3V or 5V single monochrome passive LCD panel support.

• 4/8/16-bit 3.3V or 5V single color passive LCD panel support.

• 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support.

• Direct interface for 18-bit Sharp HR-TFT LCD panel support.

• Direct interface for 18-bit Casio TFT LCD panel support.

• Direct interface for 18-bit TFT Type 2 LCD panel support

• Direct interface for 18-bit TFT Type 3 LCD panel support

• Direct interface for 18-bit TFT Type 4 (Epson ND-TFD) LCD panel support.

• Connector for USB client support.

• Oscillators for CLKI and CLKI2.

Installation and Configuration

S5U13A05P00C100 Evaluation Board Seiko Epson Corporation 7

Rev. 1.02

3 Installation and Configuration

The S5U13A05P00C100 is designed to support as many platforms as possible. The

S5U13A05P00C100 incorporates a DIP switch and three jumpers which allow both the

evaluation board and the S1D13A05 LCD controller to be configured for a specified evalu-

ation platform.

3.1 Configuration DIP Switches

The S1D13A05 has seven configuration inputs (CNF[6:0]) which are read on the rising

edge of RESET#. In order to configure the S1D13A05 for multiple Host Bus Interfaces an

eight-position DIP switch (SW1) is required. The following figure shows the location of

DIP switch SW1 on the S5U13A05P00C100.

Figure 3-1: Configuration DIP Switch (SW1) Location

DIP Switch - SW1

Installation and Configuration

8Seiko Epson Corporation S5U13A05P00C100 Evaluation Board

Rev. 1.02

All S1D13A05 configuration inputs are fully configurable using the eight position DIP

switch as described below.

Table 3-1: Configuration DIP Switch Settings

Switch

(SW1)

S1D13A05

Signal

Value on this pin at rising edge of RESET# is used to configure:

Closed (On/1) Open (Off/0)

SW1-5,

SW1-[3:1]

CNF4,

CNF[2:0]

Select host bus interface as follows:

CNF4 CNF2 CNF1 CNF0 Host Bus Interface

1 0 0 0 SH-4/SH-3 interface, Big Endian

0 0 0 0 SH-4/SH-3 interface, Little Endian

1 0 0 1 MC68K #1, Big Endian

0 001 Reserved

1 0 1 0 MC68K #2, Big Endian

0 010 Reserved

1 0 1 1 Generic #1, Big Endian

0 0 1 1 Generic #1, Little Endian

1 100 Reserved

0 1 0 0 Generic #2, Little Endian

1 1 0 1 RedCap 2, Big Endian

0 101 Reserved

1 1 1 0 DragonBall, Big Endian

0 110 Reserved

X 111 Reserved

SW1-4 CNF3 Reserved. Must be set to 1.

SW1-6 CNF5 WAIT# is active high WAIT# is active low

SW1-7 CNF6 CLKI to BCLK Divide ratio 2:1 CLKI to BCLK divide ratio 1:1

SW1-8 - Disable PCI bridge for non-PCI host Enable PCI bridge for PCI host

= Required settings when using the PCI Bridge FPGA

Installation and Configuration

S5U13A05P00C100 Evaluation Board Seiko Epson Corporation 9

Rev. 1.02

3.2 Configuration Jumpers

The S5U13A05P00C100 has three jumper blocks which configure various settings on the

board. The jumper positions for each function are shown below.

JP3 - LCD Panel Voltage

JP3 selects the voltage level to the LCD panel.

When the jumper is at position 1-2, the voltage level is +3.3V (default setting).

When the jumper is at position 2-3, the voltage level is +5.0V.

Note

When configured for Sharp HR-TFT, JP3 and JP5 must be set to position 1-2.

Figure 3-2: Configuration Jumper (JP3) Location

Table 3-2: Jumper Summary

Jumper Function Position 1-2 Position 2-3 No Jumper

JP3 LCD Panel Voltage +3.3V LCDVCC +5V LCDVCC —

JP4 PCI_IRQ Disable Enable USB IRQ on PCI — Disable USB IRQ on PCI

JP5 GP00 Polarity on H3 Normal (Active High) Inverted (Active Low) GPO0 not sent to H3

= recommended settings

+5 LCDVCC

+3.3 LCDVCC

JP3

Installation and Configuration

10 Seiko Epson Corporation S5U13A05P00C100 Evaluation Board

Rev. 1.02

JP4 - PCI_IRQ Enable

JP4 selects whether the USB IRQ on PCI is enabled or disabled.

When the jumper is at position 1-2, the USB IRQ on PCI is enabled (default setting).

When no jumper is installed, the USB IRQ on PCI is disabled.

Figure 3-3: Configuration Jumper (JP4) Location

JP5 - GPO0 Polarity on H3

JP5 selects the polarity of the GPO0 signal available on the TFT Type 3 Extended LCD

Connector H3.

When the jumper is at position 1-2, the GPO0 signal is sent directly (active high) to H3

(default setting).

When the jumper is at position 2-3, the GPO0 signal is inverted and then sent (active low)

to H3.

When no jumper is installed, GPO0 is not sent to H3.

Figure 3-4: Configuration Jumper (JP5) Location

USB IRQ USB IRQ

JP4

on PCI enabled on PCI disabled

Normal Inverted GPIO0 not

JP5

(Active High) (Active Low) sent to H1

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