HP 13255 Manuale utente

13255

MEMORY

CONTROLLER

MODULE

Manual

Part

10.

13255-912q9

1/.2S.;l

PRINTED

JUN-23-81

DATA

TERMINAL

TECHNICAL

INFORMATION

HEWLETT

ifi

PACKARD

Printed

U.S.A.

13255

Processor

(8085A-2)

Module 13255-91249/02

REV

FEB-14-82

1.0

INTRODUCTION.

The

processor

(8085A-2)

module

functions

the

controlling

unit

for

the

2747F

terminal.

also

contains

the

hardware

intertace

the

processor

the

external

keyboard.

The

processor

retches

instructions

trom

memory

and

pertorms

I/O

operations

other

.adul.s

attached

the

terminal

data

bus

(backplane

ass.bly).

!be

8085A-2

lIOdule

has

the

capability

down

code

RAM

based

2647F.

2.0

OPERATING

PARAMETERS.

A summary

operating

parameters

tor

the

Processor

(8085A-2) Module

contained

tables

1.0

through

6.7

Table

1.0

Physical

Parameter.

================================================================================

PART

Size

x Wx

Weight 1

NUMBER

NOMENCLATURE

1 +/-0.100

Inche.

1 (Pounds) 1

/==============1==============================1======================1=========1

1 I 1 1 1

I 02640-60249 I

PROCESSOR

(8085A-2)

I 12.5 x 4.0 x 0.5 1 0·5 1

1 I I 1 1

1 I 1 1 1

1==============================================================================1

I 1

NUMBER

BACKPLANE

SLOTS

REQUIRED:

1 I

================================================================================

13255

MEMORY

CONTROLLER

MODULE

Manual

Part

10.

13255-912q9

PRIM'l'ED

1/:IS-.;2

JUH-23-81

IOTlCE

The

information

contained

this

document

subject

change

without

notice.

HEWLETl'-PACKARD

MAKES

WARRANTY

AMY

KIND

WITH

REGARD

THIS

MATERIAL,

INCLUDING,

BUT

lOT

LIMITED

THE

IMPLIED

WARRANTIES

MERCHANTABILITY

AND

FITNESS

FOR

PARTICULAR

PURPOSE.

Hewlett-Packard

shall

not

liable

for

errors

contained

herein

tor

incidental

consequential

damages

connection

with

the

furnishing,

performance,

use

this

material.

This

document

contains

proprietary

information

which

protected

All

rights

are

reserved.

part

this

document

may

photocopied

reproduced

without

the

prior

written

consent

Hewlett-

Packard

Company.

c 1982 by

HEWLETT-PACKARD

COMPANY

NOTE:

This

document

part

the

2647F

DATA

TERMINAL

product

series

Technical

Information

Package

(HP

13255).

13255

Processor

(8085A-2) Module

1.0

INTRODUCTION.

13255-91249/02

REV

FEB-14-82

The

processor

(8085A-2)

aodule

functions

the

controllin,

unit

for

the

2747F

terminal.

also

contains

the

hardware

interface

the

processor

the

external

keyboard.

The

processor

f.tch

••

in.truction.

trom

memory

and

performs

I/O

operation.

other

.odul..

attached

the

terllinal

data

bus

(backplane

ass.bly).

'l'b.

8085A-2 lIOdule

has

the

capability

down

code

RAM

based

2647F.

2.0

OPERATING

PARAMETERS.

summary

operating

parameters

tor

the

Proces.or

(8085A-2) Modul.

contained

tables

1.0

through

6.7

Table

1.0

Physical

Parameters

-===============================================================================

PART

1 I

Size

x Wx D) I Weisht

NUMBER

NOMENCLATURE

+/-0.100

Inches

I (Pounds)

==============1==============================1======================1=========

1 1 I

02640-60249 I

PROCESSOR

(8085A-2) I

12.5

4.0

0.5

I I I

I 1 1

==============================================================================

NUMBER

BACKPLANE

SLOTS

REQUIRED:

================================================================================

13255

13255-91252/03

Rev JUN-23-81

Memory

Controller

Table

2.0

Reliability

and

Environmental

Information

===============================================================================-

Environmental:

( X )

Class

()

Other:

Restrictions:

Type

tested

product

level

1==============================================================================

Failure

Rate:

4.774

(percent

per

1000

hours)

--------------------------------------------------------------------------------

Table

3.0

Power

Supply

and

Clock

Requirements

-Measured

(+/-

Unless

Otherwise

Specified)

--------------------------------------------------------------------------------

-------------------------------------- ----------------------------------------

Volt

Supply

+12

Volt

Supply

-12

Volt

Supply

-42

Volt

Supply

0.5

NOT

APPLICABLE

NOT

APPLICABLE

NOT

APPLICABLE

-------------------------------------- ---------------------------------------

115

volts

220

volts

A A

NOT

APPLICABLE

NOT

APPLICABLE

------------------------------------------------------------------------------

Clock

Frequency:

4.915

MHz

================================================================================

Table

4.0

Jumper

Definition

================================================================================

PCA

Function

Designation

I I

1=============1================================================================1

1 I I

I 1 I

RAM/ROM

Based

Terminal

(see

section

3.8)

I I ,

I I I

================================================================================

13255

Memory

Controller

Table

5.0

Connector

Information

13255-91252/04

Rev

JUN-23-81

--------------------------------------------------------------------------------

Connector

Signal

and

No.

Name

Description

------------- -------------- -------------------------------------------------

P1,

+5V

Volt

Power

Supply

-2

GND

Ground

Common

Return

(Power and

Signal)

-3

SYSCLK

4.915

MHz

System

Clock

-4

Not Used

-5

ADDRO

Negative

True,

Address

Bit

-6

ADDR1

Negative

True,

Address

Bit

-1

ADDR2

Negative

True,

Address

Bit

-8

ADDR3

Negative

True,

Address

Bit

-9

ADDR4

Negative

True,

Address

Bit

-10

ADDR5

Negative

True,

Address

Bit

-11

ADDR6

Negative

True,

Address

Bit

-12

ADDR1

Negative

True,

Address

Bit

-13

ADDRa

Negative

True,

Address

Bit

-14

ADDR9

Negative

True,

Address

Bit

-15

ADDR10

Negative

True,

Address

Bit

-16

ADDR11

Negative

True,

Address

Bit

-11

ADDR12

Negative

True,

Address

Bit

-18

ADDR13

Negative

True,

Address

Bit

-19

ADDR14

Negative

True,

Address

Bit

-20

ADDR15

Negative

True,

Address

Bit

-21

Negative

True,

Input

Output/Memory

-22

GND

Ground

Common

Return

(Power and

Signal)

==============-=================================================================

13255

Memory

Controller

Table

5.0

Connector

Information

(cont)

13255-91252/05

Rev JUN-23-81

-----------------------------------------------.---------------------------------

-----------------------------

--------------------------------------------------

Connector

and

No.1

-------------

P1,

-B

-C

-D

-E

-F

-H

-J

-K

-L

-M

-N

-p

-R

-S

-T

-u

-v

-W

-x

-y

-z

Signal

Name

--------------

GND

PON

BUS

WRITE

WAIT

ADDR16

ADDR17

ADDR18

REQ

Signal

Description

-------------------------------------------------

Ground

Common

Return

(Power and

Signal)

Not Used

Positive

True,

System Power

Negative

True,

Data

Bus

Bit

Negative

True,

Data

Bus

Bit

Negative

True,

Data

Bus

Bit

Negative

True,

Data

Bus

Bit

Negative

True,

Data

Bus

Bit

Negative

True,

Data

Bus

Bit

Negative

True,

Data

Bus

Bit

Negative

True,

Data

Bus

Bit

Negative

True,

Write/Read

Type

Cycle

Not Used

Negative

True,

Assert

Wait

State

Not Used

Positive

True,

Address

Bit

Positive

True,

Address

Bit

Positive

True,

Address

Bit

Negative

True,

Request

(Bus

Data

Valid)

Not Used

-------------------------------------------------------------------------------

--------------------------------------------------------------------------------

13255

Memory

Controller

13255-91252/06

Rev JUN-23-81

3.0

FUNCTIONAL

DESCRIPTION.

Refer

the

block

diagram

(figure

1),

schematic

diagram

(figure

2 and

3),

the

timing

diagram

(figure

4),

and

the

parts

list

(02640-60252).

The

Memory

Controller

Module

provides

program

and

variable

space

for

the

terminal.

consists

memory

drivers

and

series

termination

resistors,

data

port,

memory

array,

address

multiplexer,

refresh

address

generator,

refresh

timer,

refresh

cycle

generator,

bus

interface

and

board

select

circuitry,

and

memory

cycle

generator.

3.1

SERIES

TERMINATION

RESISTORS

The

series

termination

resistors

m1n1m1ze

undershoot

terminating

the

bus

lines

with

the

line

impedance.

This

approximates

ohms

since

consists

ohm

line

with

distributed,

lumped,

and

capacitive

lo~ds.

Current

limit

protection

provided

free

which

limits

the

driver

output

two

array

inputs

are

shorted

together.

3.2

DATA

PORT

3.2.1

3.2.2

The

data

port

consists

a 74LS244

data

driver

(U46)

and

a 74LS373

data

out

transparent

latch.

This

port

enabled

whenever

BOARD

SELECT

(U53-6) and

REQ

(P1-Y)

are

both

low,

causing

U56-3

go low. The

direction

data

flow

arbitrated

WRITE

(P1-P)

the

following

manner:

WRITE

high,

then

U56-8

will

active,

resulting

data

transmission

from

the

Memory

Controller

the

data

bus.

WRITE

low,

then

U56-6

will

active,

and

the

data

flow

will

from

the

bus

the

memory

array.

Data

latched

the

output

latch

the

trail-

ing

edge

CAS,

the

COllunn

address

strobe.

The

transparent

data

latch

(U27)

allows

data

propagate

through

the

latch

prior

being

latched.

This

means

the

RAM

access

time

optimized

and

higher

speed

RAM

used,

the

memory

will

appear

correspondingly

higher

speed.

The

data

latched

that

completion

the

memory

cycle

does

not

depend on

the

completion

the

processor

memory

handshake.

13255

Memory

Controller

13255-91252/07

REV

JUN-23-81

3.3

MEMORY

ARRAY

3.3.1

3.3.2

3.3.3

3.4

3.4.1

3.4.2

3.4.3

The

memory

array

consists

thirty-two

64K

RAMS.

socketed

allow

field

upgrade

and

repair.

The

RAMs

are

The power

distribution

via

a low impedance

4-layer

board

struc-

ture.

The

ceramic

capacitors

which

supply

the

transient

current

are

organized

such

that

some

redundancy

exists.

This

allows

reliable

oper-

ation

with

one open

circuit

component.

The

memory

array

organized

four

modules

equal

size

(if

all

are

loaded).

The

entire

array

activated

the

start

memory

cycle,

which

when U71-9

goes

low. At

that

time,

a row

address

strobe

sent

all

four

banks.

The column

address

s"i;robe

passes

through

four

one

decoder

which

determines

which module

selected

for

read

write.

ADDRESS

MULTIPLEXER

The

address

multiplexer

consists

two 74LS258 quad

inverting

line

tri-state

multiplexers

(U75,76)

and

a 74LS244

octal

tri-state

buf-

fer

(U55).

The 74LS258

multiplexers

select

the

row

column

address

from

the

ter-

minal

bus

address

lines

for

memory

cycles.

Which

address

selected

determined

R/C

(delay

line

R12-2).

These

multiplexers

are

put

the

hi-Z

state

during

refresh

cycles

and

during

power

(when

refresh

occuring

continuously).

The

function

the

74LS244

buffer

either

transfer

block

the

re.fresh

address

counter

outputs

from

the

internal

address

bus.

This

buffer

enabled

whenever

refresh

cycles

are

occuring

(i.e.

refresh

cycle

power

on).

13255

Memory

Controller

13255-91252/08

REV

JUN-23-81

3.4.4

Whether

the

multiplexer

the

refresh

memory

state

controlled

a 74LS74

D-flip

flop

(U24).

This

flip

flop

can

set

the

re-

fresh

state

one

two ways:

the

power on

signal

fed

the

pre-

set

input

initialize

the

system

and

allow

for

continuous

refresh

during

power

on.

The

flip

flop

can

also

clocked

the

refresh

state

the

signal

RFSH

(U14-8)

which

indicates

the

start

refresh

cycle.

The

multiplexor

reset

the

memory

state

the

signal

RFSH

STALL

(U13-5)

the

clear

input.

This

occurs

halfway

through

the

RAS

pre

charge

time

the

refresh

cycle

allow

the

memory

ad-

dresses

sufficient

setup

time

before

the

memory

cycle.

3.5

REFRESH

ADDRESS

GENERATOR

3.6

3.6.1

The

refresh

address

generator

consists

a 74LS393

dual

four

bit

counter

(U45).

This

counter

allowed

come

indeterminant

state

and

then

continuously

clocked

through

the

128

possible

refresh

addresses.

The

eigth

bit

also

counts

although

not

necessary

refresh

address

line.

The

counter

clocked

the

signal

COUNT

(U26-

6).

COUNT

the

inverted

refresh

row

address

strobe,

and

therefore

the

refresh

address

generator

clocked

each

refresh

cycle

the

trailing

edge

the

row

address

strobe.

REFRESH

TIMER

Each row

the

dynamic memories

must

completely

refreshed

every

msec.

Since

each

memory

organized

into

128

rows,

there

must

128

refresh

cycles

every

2 msec

avoid

loss

information.

This

means

that

refresh

cycle

must

occur

every

15.63

usec.

The

system

clock

4.915

MHz.

this

clock

divided

64 and

the

resulting

edge

used

trigger

refresh

cycle,

refresh

will

occur

every

13.02

usec.

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